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CN5860-800 EXP - Cavium
<
cavium
|
octeon plus
Revision as of 00:09, 15 December 2016 by
ChipIt
(
talk
|
contribs
)
(Created page with "{{cavium title|CN5860-800 EXP}} {{mpu | name = Cavium CN5860-800 EXP | no image = | image = octeon plus chip.png | image size...")
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Template:mpu
Facts about "
CN5860-800 EXP - Cavium
"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a
container
construct and is provided by
Semantic MediaWiki
.
CN5860-800 EXP - Cavium#package
+
base frequency
800 MHz (0.8 GHz, 800,000 kHz)
+
core count
16
+
designer
Cavium
+
family
OCTEON Plus
+
first announced
October 9, 2006
+
first launched
February 2007
+
full page name
cavium/octeon plus/cn5860-800bg1521-exp
+
has ecc memory support
true
+
has hardware accelerators for data compression
true
+
has hardware accelerators for data decompression
true
+
has hardware accelerators for network quality of service processing
true
+
has hardware accelerators for regular expression
true
+
has hardware accelerators for tcp packet processing
true
+
instance of
microprocessor
+
isa
MIPS64
+
isa family
MIPS
+
l1$ size
768 KiB (786,432 B, 0.75 MiB)
+
l1d$ description
64-way set associative
+
l1d$ size
256 KiB (262,144 B, 0.25 MiB)
+
l1i$ description
64-way set associative
+
l1i$ size
512 KiB (524,288 B, 0.5 MiB)
+
l2$ description
8-way set associative
+
l2$ size
2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB)
+
ldate
February 2007
+
main image
+
manufacturer
TSMC
+
market segment
Network
+
max cpu count
1
+
max memory bandwidth
11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s)
+
max memory channels
1
+
microarchitecture
cnMIPS
+
model number
CN5860-800 EXP
+
name
Cavium CN5860-800 EXP
+
package
FCBGA-1521
+
part number
CN5860-800BG1521-EXP
+
process
90 nm (0.09 μm, 9.0e-5 mm)
+
series
CN58xx
+
smp max ways
1
+
supported memory type
DDR2-800
+
technology
CMOS
+
thread count
16
+
word size
64 bit (8 octets, 16 nibbles)
+