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From WikiChip
CN3850-600 EXP - Cavium
Template:mpu The CN3850-600 EXP is a 64-bit dodeca-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates twelve cnMIPS cores, operates at 600 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3850-600bg1521-exp&oldid=31428"
Facts about "CN3850-600 EXP - Cavium"
has ecc memory support | true + |
has hardware accelerators for data compression | true + |
has hardware accelerators for data decompression | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for regular expression | true + |
has hardware accelerators for tcp packet processing | true + |
l1$ size | 480 KiB (491,520 B, 0.469 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 96 KiB (98,304 B, 0.0938 MiB) + |
l1i$ description | 64-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR2-800 + |