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CN3120-550 NSP - Cavium
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Revision as of 01:46, 9 December 2016 by ChipIt (talk | contribs)

Template:mpu The CN3120-550 NSP is a 64-bit dual-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2006. This processor, which incorporates a two cnMIPS cores, operates at 555 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network services such as encryption, compression & decompression, RegEx engine, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.