8008 ISA
Developer	Intel Datapoint Corporation
Implementation	8008
Dev model	proprietary
Design	Von Neumann architecture
Data word size	8 bit 1 octets 2 nibbles
Instruction word size	8 bit 1 octets
Instructions	48
Introduction	1972
Version	1
Format	register-register
Endianness	bi-endian
Registers	0
GPRs	7 (scratchpad)
ISAs • By Company • By Inst • By Data

The 8008 ISA (or MCS-8 ISA) was an instruction set architecture used in the 8008 and 8008-1 microprocessors.

This ISA has an 8-bit data and address bus. This architecture included seven 8-bit registers, 48 instructions, and interrupt capability.

Registers

The 8008 had seven scratchpad registers. A few of them had additional capabilities - A is used an an accumulator register. Registers H & L are high-order and low-order words of a 14-bit address.

Register	Size	Purpose
A	8 bit	Accumulator
B	8 bit	GP
C	8 bit	GP
D	8 bit	GP
E	8 bit	GP
H	8 bit	High-order word
L	8 bit	Low-order word

ISA

Data on the 8008 is always stored in an 8-bit binary integer.

Data Word

D₇ D₅ D₄ D₃ D₂ D₁ D₀

Instructions can be made of 1-3 bytes depending on operation. Multi-byte instructions must be stored in successive order in memory. Typical operations involving register-register operations such as arithmetic and logic operations only require one byte and take the following form:

1-Byte Inst

D₇ D₅ D₄ D₃ D₂ D₁ D₀

OPCode

Instructions that involve an immediate value have 2 bytes. The first bite stores the opcode and the second byte stores the 8-bit value.

2-Byte Inst

D₇ D₅ D₄ D₃ D₂ D₁ D₀

D₇ D₅ D₄ D₃ D₂ D₁ D₀

OPCode

Imm Value

Instructions involving an address (such as CALL and JUMP) require a 14-bit address. This is done via a 3-byte instruction where the first byte is the opcode, the second byte is the low-order word, and the third byte is the high-order word. Note that the 2 MSBs on the high-order word are don't cares.

3-Byte Inst

D₇ D₅ D₄ D₃ D₂ D₁ D₀

D₇ D₅ D₄ D₃ D₂ D₁ D₀

D₇ D₅ D₄ D₃ D₂ D₁ D₀

OPCode

High-Order Add

Low-Order Add

See also

• MCS-8
• MCS-4