Page title matches

Page text matches

• intel/pentium (2009)/n3700
  ...up to 2.4 GHz. This SoC incorporates the {{intel|HD Graphics (Braswell)}} GPU which has 16 execution units and operates at 400 MHz. | gpu = HD Graphics (Braswell)
  4 KB (540 words) - 17:40, 27 March 2018
• intel/celeron/n3000
  ...ice that speed. This SoC incorporates the {{intel|HD Graphics (Braswell)}} GPU which has 12 execution units and operates at 320 MHz up to 600 MHz bursts. | gpu = HD Graphics (Braswell)
  4 KB (544 words) - 17:43, 27 March 2018
• intel/celeron/n3050
  ...up to 2.16 GHz. This SoC incorporates the {{intel|HD Graphics (Braswell)}} GPU which has 12 execution units and operates at 320 MHz with 600 MHz busts. | gpu = HD Graphics (Braswell)
  4 KB (580 words) - 09:40, 8 July 2022
• intel/celeron/n3150
  ...up to 2.08 GHz. This SoC incorporates the {{intel|HD Graphics (Braswell)}} GPU which has 12 execution units and operates at 320 MHz with up to 640 MHz bur | gpu = HD Graphics (Braswell)
  5 KB (724 words) - 06:10, 2 December 2018
• intel/celeron/n3010
  ...ode of up to 2.24 GHz. This SoC incorporates the {{intel|HD Graphics 400}} GPU which has 12 execution units and operates at 320 MHz with up to 600 MHz bur | gpu = HD Graphics 400
  4 KB (539 words) - 17:39, 27 March 2018
• intel/celeron/n3160
  ...ode of up to 2.24 GHz. This SoC incorporates the {{intel|HD Graphics 400}} GPU which has 12 execution units and operates at 320 MHz with up to 640 MHz bur | gpu = HD Graphics 400
  4 KB (535 words) - 17:39, 27 March 2018
• intel/celeron/n3060
  ...ode of up to 2.48 GHz. This SoC incorporates the {{intel|HD Graphics 400}} GPU which has 12 execution units and operates at 320 MHz with up to 600 MHz bur | gpu = HD Graphics 400
  5 KB (722 words) - 01:50, 24 November 2018
• intel/celeron/j3160
  ...ode of up to 2.24 GHz. This SoC incorporates the {{intel|HD Graphics 400}} GPU which has 12 execution units and operates at 320 MHz with up to 700 MHz bur | gpu = HD Graphics 400
  4 KB (533 words) - 17:41, 27 March 2018
• intel/celeron/j3060
  ...ode of up to 2.48 GHz. This SoC incorporates the {{intel|HD Graphics 400}} GPU which has 12 execution units and operates at 320 MHz with up to 700 MHz bur | gpu = HD Graphics 400
  4 KB (539 words) - 17:39, 27 March 2018
• intel/microarchitectures/broadwell (client)
  *** shared with GPU ({{intel|Crystal Well}}) ..., %L2$, %L3$, TDP, %Frequency, 1 Core, 2 Cores, 3 Cores, 4 Cores, Max Mem, GPU, %Frequency, Turbo}}
  14 KB (1,891 words) - 14:37, 6 January 2022
• intel/microarchitectures/haswell (client)
  ==== GPU changes ==== * Four versions of GPU options codenamed GT1, GT2, GT3 and GT3 (with GT3e having a {{intel|Crystal
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/core i7ee
  |?integrated gpu |?integrated gpu base frequency#MHz
  4 KB (572 words) - 16:03, 1 June 2017
• intel/microarchitectures/ivy bridge (client)
  * 1 GPU core ..., %L2$, %L3$, TDP, %Frequency, 1 Core, 2 Cores, 3 Cores, 4 Cores, Max Mem, GPU, %Frequency, Turbo}}
  5 KB (689 words) - 13:44, 2 May 2020
• intel/microarchitectures/sandy bridge (client)
  ...sed by the {{intel|DMI}} with the other x16 lanes designed for a dedicated GPU. The memory controller supports up to dual-channel DDR3-1600 (depending on ...on multiple requests at the same time. Agent requests (e.g., ones from the GPU) are handled by the individual cache boxes via the ring. This is much diffe
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/westmere (client)
  ..., Cores, Threads, %L2$, %L3$, TDP, %Frequency, {{intel|TBT 1.0}}, Max Mem, GPU, %Frequency, Turbo, {{x86|AES}}, vPro, VT-d, VT-x}} |?integrated gpu
  10 KB (1,258 words) - 21:07, 9 March 2018
• intel/microarchitectures/nehalem (client)
  ..., Cores, Threads, %L2$, %L3$, TDP, %Frequency, {{intel|TBT 1.0}}, Max Mem, GPU, %Frequency, Turbo, {{x86|AES}}, vPro, VT-d, VT-x}} |?integrated gpu
  4 KB (459 words) - 21:44, 26 December 2023
• intel/microarchitectures/skylake (client)
  * IGP performance - Improvement to both power and performance of the GPU ...cting the cores together is the ring interconnect. The ring extends to the GPU and the system agent as well. Intel further optimized the ring in Skylake f
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  File:2 core lp gt2 skylake.svg|Dual-core die, GT2 GPU, Low Power File:2 core lp gt3 skylake.svg|Dual-core die, GT3 GPU, Low Power
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/microarchitectures/cannon lake
  * 2 CPU cores + 40 GPU EUs
  7 KB (887 words) - 12:53, 5 August 2019
• intel/microarchitectures/ice lake (client)
  ...es on the {{intel|ring interconnect architecture}} along with {{\\|Gen11}} GPU, and an improved {{intel|System Agent}} with a new display engine and I/O. ...iding bandwidths in the range of 50-60 GB/s. Ice Lake has a new integrated GPU which is based on their {{\\|Gen11}} microarchitecture which provides a lar
  23 KB (3,613 words) - 12:31, 20 June 2021

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)