• intel/microarchitectures/bonnell
  ...reading of heat across the chip with more units. This also allows a higher clock rate. ...tour into a microcode sequencer for decoding, necessitating two additional clock cycles. Additionally there is a roughly 7 cycle penalty for correctly predi
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/pentium (2009)
  | clock min = <!-- clock min speed, e.g. "200 MHz" --> | clock max = <!-- clock max speed, e.g. "900 MHz" -->
  20 KB (2,661 words) - 00:45, 11 October 2017
• intel/celeron
  | clock min = <!-- clock min speed, e.g. "200 MHz" --> | clock max = <!-- clock max speed, e.g. "900 MHz" -->
  25 KB (3,201 words) - 03:13, 22 September 2018
• intel/xeon d
  | clock min = 1300 MHz | clock max = 2400 MHz
  13 KB (1,784 words) - 08:04, 6 April 2019
• intel/core i7ee/i7-920xm
  | bus speed = | clock multiplier = 15
  4 KB (522 words) - 20:46, 4 October 2018
• intel/core i7ee/i7-940xm
  | bus speed = | clock multiplier = 16
  4 KB (537 words) - 15:01, 13 December 2019
• intel/microarchitectures/sandy bridge (client)
  **** Read: 32 B/cycle (@ ring [[clock]]) **** Write: 32 B/cycle (@ ring clock)
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/p6
  ...to [[0.25 µm]], allowing for considerably lower voltage and higher clock speed at a smaller silicon die area. The shrink introduced a 5th metal layer whic
  3 KB (325 words) - 21:34, 22 February 2020
• intel/microarchitectures/skylake (client)
  ** DMI/PEG are now on a discrete clock domain with BCLK sitting on its own domain with full-range granularity (1 M **** Read: 32 B/cycle (@ ring [[clock]])
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  ...chitectures/skylake#.22Speed_Shift.22_.28new_power_management.29|SkyLake's Speed Shift]] implementation is significantly improved, cutting responsiveness by **** Read: 32 B/cycle (@ ring [[clock]])
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/microarchitectures/ice lake (client)
  ...port everything that was necessary (e.g., legacy [[USB 2]] as well as high speed PCIe Gen 3), the controller was connected to both the CPU and the chipset. ...orting everything from power delivery to the legacy I/O to the latest high-speed interfaces such as DisplayPort and USB 3.1.
  23 KB (3,613 words) - 12:31, 20 June 2021
• intel/core i7ee/i7-975
  | bus speed = 3200 MHz | clock multiplier = 25
  4 KB (415 words) - 16:24, 13 December 2017
• intel/core i7ee/i7-965
  | bus speed = 3200 MHz | clock multiplier = 24
  4 KB (415 words) - 16:24, 13 December 2017
• intel/core i7ee/i7-980x
  | bus speed = 3200 MHz | clock multiplier = 25
  4 KB (419 words) - 16:24, 13 December 2017
• intel/core i7ee/i7-990x
  | bus speed = 3200 MHz | clock multiplier = 26
  4 KB (414 words) - 16:24, 13 December 2017
• intel/core i7ee/i7-3960x
  | bus speed = | clock multiplier = 33
  5 KB (517 words) - 23:32, 22 September 2019
• intel/core i7ee/i7-3970x
  | bus speed = | clock multiplier = 35
  4 KB (456 words) - 16:24, 13 December 2017
• intel/core i7ee/i7-5960x
  | bus speed = | clock multiplier = 30
  5 KB (524 words) - 16:24, 13 December 2017
• intel/core i7ee/i7-6950x
  |bus speed=5 GT/s |clock multiplier=30
  4 KB (564 words) - 14:29, 24 March 2019
• intel/core i7ee/i7-3940xm
  | bus speed = | clock multiplier = 30
  5 KB (573 words) - 16:24, 13 December 2017

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