• intel/microarchitectures/sunny cove
  ** 5-Level Paging ...indow]] pipeline, a wider execution back-end, higher load-store bandwidth, lower effective access latencies, and bigger caches.
  34 KB (5,187 words) - 06:27, 17 February 2023
• arm holdings/microarchitectures/cortex-a15
  The Cortex-A15 was often combined with a number of lower power cores (e.g. {{\\|Cortex-A7}}) in a {{armh|big.LITTLE}} configuration ** Level 1 instruction cache switched to [[PIPT]] (from [[VIPT]])
  3 KB (347 words) - 14:40, 31 December 2018
• static random-access memory
  ...30,644,682 out of the 47,212,207 transistors (65%) were dedicated to the [[level 2 cache]]. In Intel's Itanium 2, codename {{intel|Montecito|l=arch}}, 90% o ...om the read buffer size. In other words, the decoupled read buffer permits lower write voltages while enabling higher read currents.
  6 KB (920 words) - 03:14, 30 December 2019
• amd/ryzen 9
  ...ntel|Core i9}} processors, offering competitive and greater performance at lower or similar prices.
  3 KB (410 words) - 01:07, 26 May 2020
• qualcomm/snapdragon 400/460
  '''Snapdragon 460''' is an entry-level {{arch|64}} [[ARM]] [[LTE]] [[system on a chip]] designed by [[Qualcomm]] a ** Lower power consumption for Bluetooth audio
  4 KB (529 words) - 22:59, 29 December 2022
• arm holdings/microarchitectures/cortex-x1
  ...hesizable core]] designed by [[Arm]]. It is delivered as Register Transfer Level (RTL) description in Verilog and is designed to be integrated into customer ...es in [[DynamIQ Shared Unit]] (DSU) cluster along with possibly with other lower-power cores such as the {{\\|Cortex-A55}} to more efficiently support a wid
  7 KB (995 words) - 14:21, 4 July 2022
• iso-
  ...ain workload conditions) over the 1st-generation for identical performance level or capabilities on the same [[process node]]. In other words, this example * '''iso-performance''' - A comparison that is done at a fixed performance level (e.g., at a fixed [[SPEC CPU2006]]/[[SPEC CPU2017|17]] score).
  4 KB (540 words) - 22:59, 30 May 2020
• arm holdings/microarchitectures/cortex-a510
  ** Lower power (Arm claims: -20% energy @ [[iso-performance]] / +10% performance @ [ ...omplex tightly integrates two Cortex-A510 cores, sharing a single common [[level 2 cache]] and vector processing unit (VPU). Like any other Arm IP, the Cort
  15 KB (2,282 words) - 11:20, 10 January 2023
• qualcomm/snapdragon 8
  ...Snapdragon 8 Series brings premium-level features not found in other lower-level series such as the [[Snapdragon 7]] and [[Snapdragon 6]]. The Snapdragon 8
  2 KB (278 words) - 15:10, 22 March 2023

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