• cavium/octeon/cn3120-400bg868-exp
  |package module 1={{packages/cavium/hsbga-868}} The '''CN3120-400 EXP''' is a {{arch|64}} [[dual-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and
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• cavium/octeon/cn3120-500bg868-exp
  |package module 1={{packages/cavium/hsbga-868}} The '''CN3120-500 EXP''' is a {{arch|64}} [[dual-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and
  4 KB (450 words) - 16:11, 13 December 2017
• cavium/octeon/cn3120-550bg868-exp
  |package module 1={{packages/cavium/hsbga-868}} The '''CN3120-550 EXP''' is a {{arch|64}} [[dual-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and
  4 KB (453 words) - 16:11, 13 December 2017
• cavium/octeon/cn3120-300bg868-scp
  |package module 1={{packages/cavium/hsbga-868}} The '''CN3120-300 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [
  4 KB (463 words) - 16:11, 13 December 2017
• cavium/octeon/cn3120-400bg868-scp
  |package module 1={{packages/cavium/hsbga-868}} The '''CN3120-400 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [
  4 KB (460 words) - 16:11, 13 December 2017
• cavium/octeon/cn3120-500bg868-scp
  |package module 1={{packages/cavium/hsbga-868}} The '''CN3120-500 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [
  4 KB (460 words) - 16:11, 13 December 2017
• cavium/octeon/cn3120-550bg868-scp
  |package module 1={{packages/cavium/hsbga-868}} The '''CN3120-550 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [
  4 KB (463 words) - 00:15, 14 March 2021
• cavium/octeon/cn3120-300bg868-cp
  |package module 1={{packages/cavium/hsbga-868}} The '''CN3120-300 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]
  4 KB (447 words) - 16:11, 13 December 2017
• cavium/octeon/cn3120-400bg868-cp
  |package module 1={{packages/cavium/hsbga-868}} The '''CN3120-400 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]
  4 KB (444 words) - 16:11, 13 December 2017
• cavium/octeon/cn3120-500bg868-cp
  |package module 1={{packages/cavium/hsbga-868}} The '''CN3120-500 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]
  4 KB (444 words) - 16:11, 13 December 2017
• cavium/octeon/cn3120-550bg868-cp
  |package module 1={{packages/cavium/hsbga-868}} The '''CN3120-550 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]
  4 KB (447 words) - 16:11, 13 December 2017
• cavium/octeon plus/cn5734-600bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 600 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5734-800bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 800 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5734-1000bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...avium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5734-900bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 900 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5734-600bg1217-sp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (398 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5734-800bg1217-sp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 800 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (398 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5734-1000bg1217-sp
  |package module 1={{packages/cavium/fcbga-1217}} ...avium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (398 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5740-600bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 600 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5740-800bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 800 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017

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