Semiconductor & Computer Engineering
| 8008 ISA | |
| Developer | Intel Datapoint Corporation |
| Implementation | 8008 |
| Dev model | Proprietary |
| Design | Von Neumann |
| Data word size | 8 bit 1 octets
2 nibbles |
| Instruction word size | 8 bit 1 octets
|
| Instructions | 48 |
| Introduction | 1972 |
| Version | 1 |
| Format | Register-Memory |
| Endianness | Bi-endian |
| Registers | 7 |
| GPRs | 7 (scratchpad) |
| ISAs • By Company • By Inst • By Data | |
The 8008 ISA (or MCS-8 ISA) was an instruction set architecture introduced by Intel in 1972 and was used in the 8008 and 8008-1 microprocessors.
This ISA has an 8-bit data and address bus. This architecture included seven 8-bit registers, 48 instructions, and interrupt capability.
Contents
Registers
The 8008 had seven scratchpad registers. A few of them had additional capabilities - A is used an an accumulator register. Registers H & L are high-order and low-order words of a 14-bit address.
| Register | Size | Purpose |
|---|---|---|
| A | 8 bit | Accumulator |
| B | 8 bit | GP |
| C | 8 bit | GP |
| D | 8 bit | GP |
| E | 8 bit | GP |
| H | 8 bit | High-order word |
| L | 8 bit | Low-order word |
ISA
Data on the 8008 is always stored in an 8-bit binary integer.
- Data WordD7 D6 D5 D4 D3 D2 D1 D0
Instructions can be made of 1-3 bytes depending on operation. Multi-byte instructions must be stored in successive order in memory. Typical operations involving register-register operations such as arithmetic and logic operations only require one byte and take the following form:
- 1-Byte InstD7 D6 D5 D4 D3 D2 D1 D0OPCode
Instructions that involve an immediate value have 2 bytes. The first bite stores the opcode and the second byte stores the 8-bit value.
- 2-Byte InstD7 D6 D5 D4 D3 D2 D1 D0D7 D6 D5 D4 D3 D2 D1 D0OPCodeImm Value
Instructions involving an address (such as CALL and JUMP) require a 14-bit address. This is done via a 3-byte instruction where the first byte is the opcode, the second byte is the low-order word, and the third byte is the high-order word. Note that the 2 MSBs on the high-order word are don't cares.
Listing
The 8008 ISA has 48 instructions broken a number of groups:
- Index Register Instructions
- Accumulator Group Instructions
- Program Counter and Stack Control Instructions
- Input/Output Instructions
- Machine Instructions
In 1972, Intel introduced their first set of mnemonics for their instructions. This original set consists of three characters which meant it could easily be encoded into a lookup table. A few years later, when they released their 8080 and its instruction set, they also revamped the 8008 mnemonics to match the 8080's ones more closely. The newer mnemonics resemble a primitive version of modern x86 mnemonics. Since 8008 programs can be found using bother mnemonics, both the "old" and the "new" mnemonics are listed below. Both mnemonics results in identical binary values.
| 8008 ISA | ||||
|---|---|---|---|---|
| Mnemonic (old) | Mnemonic (new) | Len | Opcode | Action |
| Index Register Instructions Load instructions do not affect any flag. The Inc and Dec instructions affect all flags except carry. | ||||
| LRdRs | MOV Rd, Rs | 1 | 11 DDD SSS2 | Rd = Rs |
| LRdM | MOV Rd, M | 1 | 11 DDD 1112 | Rd = Mem |
| LMRs | MOV Rs, M | 1 | 11 111 SSS2 | Mem = Rs |
| LRdI | MVI Rd, Imm | 2 | 00 DDD 1102 | Rd = Immed Value |
| LMI | MVI M, Imm | 2 | 00 111 1102 | Mem = Immed Value |
| INRd | INR Rd | 1 | 00 DDD 0002 | Rd = Rd + 1 (Rd ≠ A) |
| DCRd | DCR Rd | 1 | 00 DDD 0012 | Rd = Rd - 1 (Rd ≠ A) |
| Accumulator Group Instructions The result of an ALU instruction affect all flags. The rotation instructions only affect the carry flag. | ||||
| ADRs | ADD Rs | 1 | 01 000 SSS2 | A = A + Rs |
| ADM | ADD M | 1 | 01 000 1112 | A = A + Mem |
| ADI | ADI | 2 | 01 000 1002 | A = A + Immed Value |
| ACRs | ADC Rs | 1 | 01 001 SSS2 | A = Carry + Rs |
| ACM | ADC M | 1 | 01 001 1112 | A = Carry + Mem |
| ACI | ACI | 2 | 00 001 1002 | A = Carry + Immed Value |
| SURs | SUB Rs | 1 | 10 010 SSS2 | A = A - Rs |
| SUM | SUB M | 1 | 10 010 1112 | A = A - Mem |
| SUI | SUI | 2 | 00 010 1002 | A = A - Immed Value |
| SBRs | SBB Rs | 1 | 10 011 SSS2 | A = A - (Carry + Rs) |
| SBM | SBB M | 1 | 10 011 1112 | A = A - (Carry + Mem) |
| SBI | ACI | 2 | 00 011 1002 | A = A - (Carry + Immed Value) |
| NDRs | ANA Rs | 1 | 10 100 SSS2 | A = A ∧ Rs |
| NDM | ANA M | 1 | 10 100 1112 | A = A ∧ Mem |
| NDI | ANI | 2 | 00 100 1002 | A = A ∧ Immed Value |
| XRRs | XRA Rs | 1 | 10 101 SSS2 | A = A ⊕ Rs |
| XRM | XRA M | 1 | 10 101 1112 | A = A ⊕ Mem |
| XRI | XRI | 2 | 00 101 1002 | A = A ⊕ Immed Value |
| ORRs | ORA Rs | 1 | 10 110 SSS2 | A = A ∨ Rs |
| ORM | ORA M | 1 | 10 110 1112 | A = A ∨ Mem |
| ORI | ORI | 2 | 00 110 1002 | A = A ∨ Immed Value |
| CRRs | CMP Rs | 1 | 10 111 SSS2 | Compare A with Rs, set flags |
| CRM | CMP M | 1 | 10 111 1112 | Compare A with Mem, set flags |
| CRI | CPI | 2 | 00 111 1002 | Compare A with Immed Value, set flags |
| RLC | RLC | 1 | 00 000 0102 | Rotate A Left Once |
| RRC | RRC | 1 | 00 001 0102 | Rotate A Right Once |
| RAL | RAL | 1 | 00 010 0102 | Rotate A Left Through Carry Once |
| RAR | RAR | 1 | 00 011 0102 | Rotate A Right Through Carry Once |
| Program Counter and Stack Control Instructions | ||||
| JMP | JMP | 3 | 01 XXX 1002 | Unconditional Jump to immed address |
| JFC | JNC | 3 | 01 000 0002 | If carry = 0, jump to immed address |
| JFZ | JNZ | 3 | 01 001 0002 | If result ≠ 0, jump to immed address |
| JFS | JP | 3 | 01 010 0002 | If sign = 0 (positive), jump to immed address |
| JFP | JPO | 3 | 01 011 0002 | If parity = 0 (odd), jump to immed address |
| JTC | JC | 3 | 01 100 0002 | If carry = 1, jump to immed address |
| JTZ | JZ | 3 | 01 101 0002 | If result = 0, jump to immed address |
| JTS | JM | 3 | 01 110 0002 | If sign = 1 (negative), jump to immed address |
| JTP | JPE | 3 | 01 111 0002 | If parity = 1 (even), jump to immed address |
| CAL | CALL | 3 | 01 XXX 1102 | Save current address onto the stack and jump to immed address |
| CFC | CNC | 3 | 01 000 0102 | If carry = 0, save current address and jump to immed address |
| CFZ | CNZ | 3 | 01 001 0102 | If result ≠ 0, save current address and jump to immed address |
| CFS | CP | 3 | 01 010 0102 | If sign = 0 (positive), save current address and jump to immed address |
| CFP | CPO | 3 | 01 011 0102 | If parity = 0 (odd), save current address and jump to immed address |
| CTC | CC | 3 | 01 100 0102 | If carry = 1, save current address and jump to immed address |
| CTZ | CZ | 3 | 01 101 0102 | If result = 0, save current address and jump to immed address |
| CTS | CM | 3 | 01 110 0102 | If sign = 1 (negative), save current address and jump to immed address |
| CTP | CPE | 3 | 01 111 0102 | If parity = 1 (even), save current address and jump to immed address |
| RET | RET | 1 | 00 XXX 1112 | Unconditionally return, down one stack level |
| RFC | RNC | 1 | 00 000 0112 | If carry = 0, return, down one stack level |
| RFZ | RNZ | 1 | 00 001 0112 | If result ≠ 0, return, down one stack level |
| RFS | RP | 1 | 00 010 0112 | If sign = 0 (positive), return, down one stack level |
| RFP | RPO | 1 | 00 011 0112 | If parity = 0 (odd), return, down one stack level |
| RTC | RC | 1 | 00 100 0112 | If carry = 1, return, down one stack level |
| RTZ | RZ | 1 | 00 101 0112 | If result = 0, return, down one stack level |
| RTS | RM | 1 | 00 110 0112 | If sign = 1 (negative), return, down one stack level |
| RTP | RPE | 1 | 00 111 0112 | If parity = 1 (even), return, down one stack level |
| RST | RST | 1 | 00 AAA 1012 | Call the subroutine at memory AAA000 (up one stack level) |
| Input/Output Instructions | ||||
| INP | IN | 1 | 01 00M MM12 | A = PORT[MMM] |
| OUT | OUT | 1 | 01 RRM MM12 | PORT[RRMMM] = A (RR ≠ 00) |
| Machine Instructions | ||||
| HLT | HLT | 1 | 00 000 00X2 | Enter STOPPED state; remain there until interrupted |
| HLT | HLT | 1 | 11 111 1112 | Enter STOPPED state; remain there until interrupted |
See also
| designer | Intel + and Datapoint Corporation + |
| first launched | 1972 + |
| full page name | intel/mcs-8/isa + |
| implementation | 8008 - Intel + |
| instance of | instruction set architecture + |
| instruction count | 48 + |
| instruction word size | 8 bit (1 octets) + |
| name | 8008 + |
| word size | 8 bit (1 octets, 2 nibbles) + |