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    CN5840-1000 SCP  - Cavium    
                	
														Template:mpu CN5840-1000 SCP is a 64-bit octa-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2007. This processor, which incorporates eight cnMIPS cores, operates at 1000 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration.
Contents
Cache
- Main article: cnMIPS § Cache
|  | Cache Organization  Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. | ||||||||||||||||||||||||
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Memory controller
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Expansions
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Networking
|  | Networking | |||||||
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Hardware Accelerators
[Edit/Modify Accelerators Info]
|  | Hardware Accelerators | |||||||||||
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Block diagram
Datasheet
Facts about "CN5840-1000 SCP  - Cavium"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN5840-1000 SCP - Cavium#package + | 
| base frequency | 1,000 MHz (1 GHz, 1,000,000 kHz) + | 
| core count | 8 + | 
| designer | Cavium + | 
| family | OCTEON Plus + | 
| first announced | October 9, 2006 + | 
| first launched | February 2007 + | 
| full page name | cavium/octeon plus/cn5840-1000bg1521-scp + | 
| has ecc memory support | true + | 
| has hardware accelerators for cryptography | true + | 
| has hardware accelerators for network quality of service processing | true + | 
| has hardware accelerators for tcp packet processing | true + | 
| instance of | microprocessor + | 
| isa | MIPS64 + | 
| isa family | MIPS + | 
| l1$ size | 384 KiB (393,216 B, 0.375 MiB) + | 
| l1d$ description | 64-way set associative + | 
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l1i$ description | 64-way set associative + | 
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + | 
| l2$ description | 8-way set associative + | 
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + | 
| ldate | February 2007 + | 
| main image |  + | 
| manufacturer | TSMC + | 
| market segment | Network + | 
| max cpu count | 1 + | 
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + | 
| max memory channels | 1 + | 
| microarchitecture | cnMIPS + | 
| model number | CN5840-1000 SCP + | 
| name | Cavium CN5840-1000 SCP + | 
| package | FCBGA-1521 + | 
| part number | CN5840-1000BG1521-SCP + | 
| process | 90 nm (0.09 μm, 9.0e-5 mm) + | 
| series | CN58xx + | 
| smp max ways | 1 + | 
| supported memory type | DDR2-800 + | 
| technology | CMOS + | 
| thread count | 8 + | 
| word size | 64 bit (8 octets, 16 nibbles) + | 
