Template:mpu The Intel Core i5-5675C is a quad core 64-bit microprocessor introduced by Intel in 2015. The microprocessor is based on the Broadwell microarchitecture, manufactured using 14nm process and incorporates the Iris Pro Graphics 6200. This MPU has support for configurable TDP down mode allowing downclocking it to 2.1GHz with 37W TDP.

Cache

Main article: Broadwell § Cache

Cache Info [Edit Values]
L1I$	128 KiB 131,072 B 0.125 MiB	4x32 KiB 8-way set associative (per core, write-back)
L1D$	128 KiB 131,072 B 0.125 MiB	4x32 KiB 8-way set associative (per core, write-back)
L2$	1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB	4x256 KiB 8-way set associative (per core, write-back)
L3$	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	12-way set associative (shared)

Graphics

Integrated Graphic Information
GPU	Intel Iris Pro Graphics 6200
Displays	3
Frequency	300 MHz 0.3 GHz 300,000 KHz
Max frequency	1100 MHz 1.1 GHz 1,100,000 KHz
Max memory	1700 MiB 1,740,800 KiB 1,782,579,200 B 1.66 GiB
Output	DisplayPort, Embedded DisplayPort, HDMI, VGA, DVI
DirectX	11.2
OpenGL	4.3
OpenCL	2.0
HDMI	1.4a
DP	1.2
eDP	1.3
Max HDMI Res	4096x2304 @24 Hz
Max DP Res	3840x2160 @60 Hz
Max eDP Res	3840x2160 @60 Hz
Max VGA Res	1920x1200 @60 Hz

Memory controller

Integrated Memory Controller
Type	DDR3L-1333, DDR3L-1600, DDR3L-1866
Controllers	1
Channels	2
ECC Support	No
Max bandwidth	25,600 MB/s
Max memory	32,768 MB

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions F16C 16-bit Floating Point Conversion NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology TSX Transactional Synchronization Extensions