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Xeon E5-4628L v4 - Intel
Template:mpu The Xeon E5-4628L v4 is a 64-bit tetradeca-core x86 microprocessor introduced by Intel in 2016. This embedded MPU is designed for low-power 4S environments. Operating at 1.8 GHz with a turbo boost frequency of 2.2 GHz for a single active core, this MPU has a TDP of 75 W and is manufactured on a 14 nm process (based on Broadwell).
Cache
- Main article: Broadwell § Cache
Cache Info [Edit Values] | ||
L1I$ | 448 KiB 458,752 B 0.438 MiB |
14x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 448 KiB 458,752 B 0.438 MiB |
14x32 KiB 8-way set associative (per core, write-back) |
L2$ | 3.5 MiB 3,584 KiB 3,670,016 B 0.00342 GiB |
14x256 KiB 8-way set associative (per core, write-back) |
L3$ | 35 MiB 35,840 KiB 36,700,160 B 0.0342 GiB |
14x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics
This microprocessor has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller | |
Type | DDR4-2133 |
Controllers | 1 |
Channels | 4 |
ECC Support | Yes |
Max bandwidth | 63.58 GiB/s |
Bandwidth (single) | 15.89 GiB/s |
Bandwidth (dual) | 31.79 GiB/s |
Max memory | 1,536 GiB |
Physical Address Extensions | 46 bit |
Expansions
Features
Facts about "Xeon E5-4628L v4 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E5-4628L v4 - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1d$ description | 8-way set associative + |
l1d$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 3.5 MiB (3,584 KiB, 3,670,016 B, 0.00342 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 35 MiB (35,840 KiB, 36,700,160 B, 0.0342 GiB) + |
max pcie lanes | 40 + |