Template:mpu
The CN3120-550 NSP is a 64-bit dual-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2006. This processor, which incorporates a two cnMIPS cores, operates at 555 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network services such as encryption, compression & decompression, RegEx engine, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
Cache
- Main article: cnMIPS § Cache
[Edit/Modify Cache Info]
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Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.
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L1$ | 80 KiB 81,920 B 0.0781 MiB
| L1I$ | 64 KiB 65,536 B 0.0625 MiB
| 2x32 KiB | 4-way set associative | |
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L1D$ | 16 KiB 16,384 B 0.0156 MiB
| 2x8 KiB | 64-way set associative | Write-through |
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| L2$ | 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB
| | | 1x256 KiB | 8-way set associative | |
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Memory controller
[Edit/Modify Memory Info]
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Integrated Memory Controller
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Max Type | DDR2-667 |
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Supports ECC | Yes |
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Max Mem | 4 GiB |
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Controllers | 1 |
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Channels | 1 |
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Width | 64 bit |
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Max Bandwidth | 4.97 GiB/s 5,089.28 MiB/s 5.336 GB/s 5,336.497 MB/s 0.00485 TiB/s 0.00534 TB/s
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Bandwidth |
Single 4.97 GiB/s
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Optional low-latency controller for content-based processing and meta data
[Edit/Modify Memory Info]
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Integrated Memory Controller
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Max Type | DDR2-667 |
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Supports ECC | Yes |
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Max Mem | 2 GiB |
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Controllers | 1 |
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Channels | 1 |
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Width | 16 bit |
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Max Bandwidth | 1.24 GiB/s 1,269.76 MiB/s 1.331 GB/s 1,331.44 MB/s 0.00121 TiB/s 0.00133 TB/s
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Bandwidth |
Single 1.24 GiB/s
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Expansions
Networking
Hardware Accelerators
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Encryption | Hardware Implementation | Yes |
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Types | DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH |
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RegEx | RegEx | Yes |
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Features | 8 Engines |
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Compression | Compression | Yes |
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Decompression | Yes |
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Block diagram
Datasheet