Template:mpu Ryzen 5 1500X is a 64-bit quad-core mid-range performance x86 desktop microprocessor set to be introduced by AMD in early 2017. This processor is based on AMD's Zen microarchitecture and is fabricated on a 14 nm process. The 1500X operates at a base frequency of 3.5 GHz with a TDP of 65 W and a Boost frequency of 3.8 GHz. This MPU supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 384 KiB 393,216 B 0.375 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 4x64 KiB 4-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative write-back L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     4x512 KiB 8-way set associative write-back L3$ 16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB     2x8 MiB 16-way set associative