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CN5750-1000 SP - Cavium
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Template:mpu CN5750-1000 SP is a 64-bit dodeca-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.

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Facts about "CN5750-1000 SP - Cavium"
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CN5750-1000 SP - Cavium#io +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
l1$ size576 KiB (589,824 B, 0.563 MiB) +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
max pcie lanes8 +
supported memory typeDDR2-800 +