Semiconductor & Computer Engineering
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CN5750-800 SSP - Cavium
Template:mpu CN5750-800 SSP is a 64-bit dodeca-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 800 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.
Facts about "CN5750-800 SSP - Cavium"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN5750-800 SSP - Cavium#io + |
| has ecc memory support | true + |
| has hardware accelerators for cryptography | true + |
| has hardware accelerators for data compression | true + |
| has hardware accelerators for data decompression | true + |
| has hardware accelerators for network quality of service processing | true + |
| has hardware accelerators for tcp packet processing | true + |
| has hardware raid 5 support | true + |
| has hardware raid 6 support | true + |
| l1$ size | 576 KiB (589,824 B, 0.563 MiB) + |
| l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 8 + |
| supported memory type | DDR2-800 + |