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CN5740-1000 SP - Cavium
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Facts about "CN5740-1000 SP - Cavium"
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CN5740-1000 SP - Cavium#package + and CN5740-1000 SP - Cavium#io +
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
core count8 +
designerCavium +
familyOCTEON Plus +
first announcedJune 26, 2007 +
first launchedAugust 2007 +
full page namecavium/octeon plus/cn5740-1000bg1217-sp +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size384 KiB (393,216 B, 0.375 MiB) +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateAugust 2007 +
main imageFile:Octeon CN57xx.svg +
manufacturerTSMC +
market segmentStorage +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
max pcie lanes8 +
microarchitecturecnMIPS +
model numberCN5740-1000 SP +
nameCavium CN5740-1000 SP +
packageFCBGA-1217 +
part numberCN5740-1000BG1217-SP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN57xx +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count8 +
word size64 bit (8 octets, 16 nibbles) +