From WikiChip
CN5750-800 SSP - Cavium
< cavium‎ | octeon plus
Revision as of 20:43, 28 December 2016 by ChipIt (talk | contribs) (Created page with "{{cavium title|CN5750-800 SSP}} {{mpu | name = Cavium CN5750-800 SSP | no image = | image = Octeon CN57xx.svg | image size =...")
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)

Template:mpu

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon_plus/cn5750-800bg1217-ssp&oldid=32246"
Facts about "CN5750-800 SSP - Cavium"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN5750-800 SSP - Cavium#io +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
l1$ size576 KiB (589,824 B, 0.563 MiB) +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
max pcie lanes8 +
supported memory typeDDR2-800 +