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From WikiChip
CN5734-1000 SSP - Cavium
< cavium | octeon plus
Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon_plus/cn5734-1000bg1217-ssp&oldid=32225"
Facts about "CN5734-1000 SSP - Cavium"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN5734-1000 SSP - Cavium#io + |
has ecc memory support | true + |
has hardware accelerators for cryptography | true + |
has hardware accelerators for data compression | true + |
has hardware accelerators for data decompression | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
has hardware raid 5 support | true + |
has hardware raid 6 support | true + |
l1$ size | 288 KiB (294,912 B, 0.281 MiB) + |
l1d$ size | 96 KiB (98,304 B, 0.0938 MiB) + |
l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 8 + |
supported memory type | DDR2-800 + |