From WikiChip
CN5840-900 SCP - Cavium
Cache
- Main article: cnMIPS § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||
|
Memory controller
![]() |
Integrated Memory Controller
|
|||||||||||||
|
Expansions
![]() |
Expansion Options
|
|||||||||||||||
|
Networking
![]() |
Networking
|
|||||||
|
Facts about "CN5840-900 SCP - Cavium"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN5840-900 SCP - Cavium#package + |
base frequency | 900 MHz (0.9 GHz, 900,000 kHz) + |
core count | 8 + |
designer | Cavium + |
family | OCTEON Plus + |
first announced | October 9, 2006 + |
first launched | February 2007 + |
full page name | cavium/octeon plus/cn5840-900bg1521-scp + |
has ecc memory support | true + |
has hardware accelerators for cryptography | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
instance of | microprocessor + |
isa | MIPS64 + |
isa family | MIPS + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 64-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
ldate | February 2007 + |
main image | ![]() |
manufacturer | TSMC + |
market segment | Network + |
max cpu count | 1 + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 1 + |
microarchitecture | cnMIPS + |
model number | CN5840-900 SCP + |
name | Cavium CN5840-900 SCP + |
package | FCBGA-1521 + |
part number | CN5840-900BG1521-SCP + |
process | 90 nm (0.09 μm, 9.0e-5 mm) + |
series | CN58xx + |
smp max ways | 1 + |
supported memory type | DDR2-800 + |
technology | CMOS + |
thread count | 8 + |
word size | 64 bit (8 octets, 16 nibbles) + |