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CN3840-400 NSP - Cavium
< cavium‎ | octeon
Revision as of 19:56, 10 December 2016 by ChipIt (talk | contribs)

Template:mpu The CN3840-400 NSP is a 64-bit octa-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2005. This processor, which incorporates eight cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

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Facts about "CN3840-400 NSP - Cavium"
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has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
l1$ size320 KiB (327,680 B, 0.313 MiB) +
l1d$ description64-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description64-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
supported memory typeDDR2-800 +