Template:mpu The CN3120-500 NSP is a 64-bit dual-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2006. This processor, which incorporates a two cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware accelerators for network services such as encryption, compression & decompression, RegEx engine, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 80 KiB 81,920 B 0.0781 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 4-way set associative   L1D$ 16 KiB 16,384 B 0.0156 MiB 2x8 KiB 64-way set associative Write-through L2$ 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB     1x128 KiB 8-way set associative