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cnMIPS - Microarchitectures - Cavium
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Revision as of 22:11, 6 December 2016 by ChipIt (talk | contribs) (Created page with "{{cavium title|cnMIPS|arch}} '''cnMIPS''' or '''cnMIPS64''' is a microarchitecture implementing the {{mips|MIPS64}} ISA designed by Cavium for their {{cavium|Octeon}}...")
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cnMIPS or cnMIPS64 is a microarchitecture implementing the MIPS64 ISA designed by Cavium for their Octeon family of processors. The "cn" stands for "Cavium Networks" or "content networking".

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Facts about "cnMIPS - Microarchitectures - Cavium"
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codenamecnMIPS +
core count2 + and 4 +
designerCavium +
first launchedSeptember 13, 2004 +
full page namecavium/microarchitectures/cnmips +
instance ofmicroarchitecture +
instruction set architectureMIPS64 +
manufacturerTSMC +
microarchitecture typeCPU +
namecnMIPS +
pipeline stages5 +
process130 nm (0.13 μm, 1.3e-4 mm) +