Semiconductor & Computer Engineering
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HiSilicon
Kirin 9000E, 9000L, 9000 5G/4G series
Kirin 9000 is HiSilicon's first SoC based on 5 nm+ FinFET (EUV) TSMC technology (N5 node)
This octa-core system on a chip is based on the 9th Gen of the HiSilicon Kirin
- series and is equipped with 15.3 billion transistors in a 1+3+4 core configuration:
- 4x ARM Cortex-A77 CPU (1x 3.13 GHz and 3x 2.54 GHz),
- 4x ARM Cortex-A55 (4x 2.05 GHz) and
- 24-core Mali-G78 GPU (22-core in the Kirin 9000E version)
The Kirin 9000L uses a 1+2+3 core configuration:
- 3x ARM Cortex-A77 (1x 3.13 GHz and 2x 2.54 GHz),
- 3x ARM Cortex-A55 (3x 2.05 GHz) and
- 22-core Mali-G78 GPU with Kirin Gaming + 3.0 implementation
- Spec
- GPU
- Kirin 9000L: ARM Mali-G78 MP22
- Kirin 9000E: ARM Mali-G78 MP22
- Kirin 9000: ARM Mali-G78 MP24
- Da Vinci NPU architecture 2.0
- Kirin 9000L: 1x Big Core + 1x Tiny Core
- Kirin 9000E: 1x Big Core + 1x Tiny Core
- Kirin 9000: 2x Big Cores + 1x Tiny Core
| Model number | Fab node | CPU | GPU | Memory technology | Sampling availability | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| ISA | µarch | Cores | Freq (GHz) | µarch | Freq (MHz) |
Type | Bus width (bit) |
Band width (GB/s) | |||
| Kirin 9000L | TSMC 5 nm+ FinFET (EUV) |
ARM v8.2-A |
Cortex-A77 Cortex-A55 (big.LITTLE) |
(1+2)+3 | 3.13 (A77 H) 2.54 (A77 L) 2.05 (A55) |
Mali-G78 MP22 |
759 MHz (1068.7 GFLOPS in FP32) |
LPDDR4X -2133 LPDDR5 -2750 |
64-bit (4x16-bit) Quad-channel |
LPDDR4X (34.1 GB/s) LPDDR5 (44.0 GB/s) |
Q4 2020 |
| Kirin 9000E | (1+3)+4 | ||||||||||
| Kirin 9000 (Hi36A0V101) Kirin 9000 4G Kirin 9000 5G |
Mali-G78 MP24 |
759 MHz (1165.8 GFLOPS in FP32) | |||||||||
Kirin 9000S, 9010, 9020 series
The Kirin 9000S, Kirin 9000S1, and Kirin 9010 of the Kirin 9000 (Hi36A0) family are the first HiSilicon-developed
- SoCs manufactured in high volumes in mainland China by SMIC.
| Model number | Fab node | CPU | GPU | Memory technology | Sampling availability | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| ISA | µarch | Cores (total) Threads (total) |
Freq (GHz) | µarch | Freq (MHz) |
Type | Bus width (bit) |
Band width (GB/s) | |||
| Kirin 9000S (Hi36A0V120) |
SMIC 7 nm FinFET |
ARMv8.x | HiSilicon Taishan, Cortex-A510 |
1+3+4 (8) 2+6+4 (12) |
2.62 GHz (TaishanV120) 2.15 GHz (TaishanV120) 1.53 GHz (Cortex-A510) |
HiSilicon Maleoon 910 |
750 MHz |
LPDDR5 -6400 LPDDR5X -8533 |
64-bit (4x16-bit) Quad- channel |
LPDDR5 (51.2 MB/s) LPDDR5X (68.2 MB/s) |
Q3 2023 |
| Kirin 9000S1 (Hi36A0V120) |
2.49 GHz (TaishanV120) 2.15 GHz (TaishanV120) 1.53 GHz (Cortex-A510) |
Q1 2024 | |||||||||
| Kirin 9000W (Hi36A0V120) |
Q4 2023 | ||||||||||
| Kirin 9000WL (Hi36A0V120) |
Q2 2024 | ||||||||||
| Kirin 9000WE (Hi36A0V120) |
Q2 2024 | ||||||||||
| Kirin T90 (Hi36A0V120) |
Q3 2024 | ||||||||||
| Kirin T90A (Hi36A0V120) |
Q3 2024 | ||||||||||
| Kirin 9000SL (Hi36A0V120) |
1+2+3 (6) 2+4+3 (9) |
2.35 GHz (TaishanV120) 2.15 GHz (TaishanV120) 1.53 GHz (Cortex-A510) |
Q4 2023 | ||||||||
| Kirin 9000WM (Hi36A0V120) |
Q2 2024 | ||||||||||
| Kirin 9010 (Hi36A0V121) |
1+3+4 (8) 2+6+4 (12) |
2.30 GHz (TaishanV121) 2.18 GHz (TaishanV120) 1.55 GHz (Cortex-A510) |
Q2 2024 | ||||||||
| Kirin 9010E (Hi36A0V121) |
2.19 GHz (TaishanV121) 2.18 GHz (TaishanV120) 1.55 GHz (Cortex-A510) |
Q3 2024 | |||||||||
| Kirin 9010A (Hi36A0V121) |
Q3 2024 | ||||||||||
| Kirin 9010W (Hi36A0V121) |
Q3 2024 | ||||||||||
| Kirin T91 (Hi36A0V121) |
Q3 2024 | ||||||||||
| Kirin 9010L (Hi36A0V121) |
1+2+3 (6) 2+4+3 (9) |
2.19 GHz (TaishanV121) 2.18 GHz (TaishanV120) 1.40 GHz (Cortex-A510) |
Q2 2024 | ||||||||
| Kirin 9020 (Hi36C0V110) |
HiSilicon Taishan |
1+3+4 (8) 2+6+4 (12) |
2.50 GHz (TaishanV123) 2.15 GHz (TaishanV120) 1.60 GHz (Taishan-Little) |
HiSilicon Maleoon 920 |
840 MHz |
Q4 2024 | |||||
| Kirin T92 (Hi36C0V110) |
Q4 2024 | ||||||||||
- ↑ (16 September 2021) Kirin 9000.