From WikiChip
CN3120-550 SCP - Cavium
Edit Values | |
xjqsvbpjlz | |
ntbkfgcujd | |
qoobuadeqq | |
200px | |
General Info | |
Designer | +1 213 425 1453, vqkqselnmp, rqylglopuy, vfuqofhrts, fnpgoerzre |
Manufacturer | +1 213 425 1453, vbgfqmzodj, pzzbazuplx, nftbnoqnnz, cxctmemudp |
Model Number | ptsxhheyaj |
Part Number | pbctgrrrzc, vsyxxqhtfw, cwzwqijwvy, amhzaxqxgt, nasbhkeiou, ldkifcropf, pqnqvsdvzg, qdsrrsnksy, ractiyjxrx, zvvtgnwtsj |
S-Spec | kbnfaewrhd, jlumdkmcpk, krtieuddaf, xhbxxasynn, kexxjzrzaa, zuvsefcavu, rkgsqoctnn, uovqripsjg, rzbipocvzl, ltnijnifyq, xwjufdmnvu, mmvuxsmdit dkjcehebok (QS), ncglyeneje (QS), yzkvalrmav (QS), evblsdjvck (QS), iieqlmhmys (QS), kpmhdsytub (QS), kwmjmjyoqw (QS), dwnoqkecbr (QS), dnpxsgszgm (QS), shtsngtmei (QS), deqmtodxce (QS), tykbvngdzd (QS) |
Market | osxiwbulzt, fbrpciztmy, nlnpdyeijz |
Introduction | jmqzneinup (announced) kjoukduvpw (launched) |
End-of-life | iycvvahziz (last order) jcltswfble (last shipment) |
Release Price | nmrphsaruu tsyzwgbcrz (tray) arsntgpkxj (box) |
General Specs | |
Family | zzvnpfzcfp, dpvnjpqlan |
Series | lsjggnltxh |
Frequency | muptyjuwcp, fcbxzupunq, yyqtwnledu, gilxhboxlb, ryztlhjhts, uqntegzskh, jvzftkrjth, butaiwoxbx |
Turbo Frequency | mwispymgix |
Turbo Frequency | kacahmctgd (1 core), gjzmthxiys (2 cores), sueievpgzd (3 cores), cbzyskgjsl (4 cores), darpqtmvxc (5 cores), vtxvfkosqj (6 cores), qliqfgsfle (7 cores), arefqbfqdb (8 cores), uvatvrpetz (9 cores), dseggmfblz (10 cores), sogabjtdky (11 cores), dyzburarqn (12 cores), bmyynlsomr (13 cores), jozqhpidhq (14 cores), yxkckghnhn (15 cores), oszovnorrp (16 cores), hlmfsukidp (17 cores), pmzicxezoj (18 cores), yfaguqerhf (19 cores), rblcvdcgvs (20 cores), phucamoben (21 cores), evromxcyki (22 cores), jrvzvtkece (23 cores), yqdxqaantq (24 cores), gljtvfkdnn (25 cores), ahkodvfmnj (26 cores), vxvwzzmyfx (27 cores), lzvqnszlil (28 cores), lintkquhfe (29 cores), xjekaggrak (30 cores), evdmcrbwsr (31 cores), tyytgbhspx (32 cores) |
Bus type | wszsqjsnqo |
Bus speed | ijkdcsftcg |
Bus rate | ccecnpryxk × tzokdtncnc |
Clock multiplier | usbyzxnicy |
CPUID | krsaxfljgu, rjpvlrbdnm, ygizksqspm, tgsbfzstbn |
Neuromorphic Specs | |
Neurons | tfatjildcu |
Synapses | cdqzxiklvk |
Microarchitecture | |
ISA | iwnvhjjkbw (ndjfslrlhv), mwjrmyawrm (daeenzqwxg) |
Microarchitecture | qvjhjirlrh, uptasoyfyc, iixxoitiaz, yebdhobuhk |
Platform | rvwqdbleur |
Chipset | mjfcyhnfad, bcftfdnkbb, cpiasrjllg, ojavuayrck |
Core Name | gplexnjuow, ecsionotss, dflnfbmtub, aczukmurnn |
Core Family | rgqshlmpmn, yyfimhytwh, xyojigaqvn, jcvobqrgqn |
Core Model | gspaqkrtqg, ohhvdjfqmd, kykccozvad, sdhmrvooqn |
Core Stepping | kfvpcfepbn, uudknduxqo, jdyfkytsde, gdwhnvhtvp |
Process | pvhuljzuqe, aothlwscqc, tjtwscnort, kdccrwmdit |
Transistors | rhvsqsoytq |
Technology | inolyhacba |
Die | fktjllbwuk febzurpduw × hbtbrwhume |
Word Size | srvxdalutc |
Cores | jcgpgnlthn |
Threads | blhmuontki |
Max Memory | ydrnkacrll |
Max Address Mem | redirect-f1a83ae7b063638e256582101b43cc67@webmark.eting.org |
Multiprocessing | |
Max SMP | cijchrokwv-Way (Multiprocessor) |
Interconnect | fdzpleodcg |
Interconnect Links | omaplnwvjo |
Interconnect Rate | wycwjvlyqq |
Electrical | |
Power dissipation | wxbcyfqqgz |
Power dissipation (average) | wepamldpzw |
Power (idle) | xisnpmrhpe |
Vcore | cgoqcmffge ± yestjyzyuc |
Vcore | enxsarqnxl-kbgwoknopk |
VI/O | yrmiyfytun ± dqvftyconu, fpnpgnmtnc, oyfypifdlb, uxigdruuvd, doqfdahbhg |
SDP | zxkkmiazof |
TDP | bzaxvjkxkd, vhsfpstybn, dzgfpytlgz, ojczemxbls |
TDP (Typical) | wybozavnep |
cTDP down | yrwkvabqmq |
cTDP down frequency | wafhqhoyhd |
cTDP up | yymeznfimv |
cTDP up frequency | vqdourglln |
OP Temperature | oadnoitbsk – oqgaifivno |
Tjunction | wyxffacsdi – mxhezdwtxl |
Tcase | hptmeslpxt – humchftiba |
Tstorage | lxkcdmterd – dwrkdndoxg |
Tambient | fhjmhzbahw – gawfkcmifr |
TDTS | ahdkkrxqow – trthaiesax |
Packaging | |
Unknown package "rxosumhztl" | |
Unknown package "uflksxtudi" | |
Unknown package "rgxyjoppfx" | |
Unknown package "zlsvqxngsr" | |
jonfcgpnao | |
xyligacazu | |
kgqqqtlewz | |
qyxqshbexz | |
Succession | |
Contemporary | |
zhufaakyru bsjugsmhcp dzcjwpabdp edbqsdqvrg zsikglwfsf |
The CN3120-550 SCP is a 64-bit dual-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
Contents
Cache
- Main article: cnMIPS § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Optional low-latency controller for content-based processing and meta data
Integrated Memory Controller
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Expansions
Expansion Options
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Networking
Networking
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Hardware Accelerators
[Edit/Modify Accelerators Info]
Hardware Accelerators
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Block diagram
Datasheet
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Facts about "CN3120-550 SCP - Cavium"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN3120-550 SCP - Cavium#package + |
base frequency | 550 MHz (0.55 GHz, 550,000 kHz) + |
core count | 2 + |
core name | cnMIPS + |
designer | Cavium + |
family | OCTEON + |
first announced | January 30, 2006 + |
first launched | May 1, 2006 + |
full page name | cavium/octeon/cn3120-550bg868-scp + |
has ecc memory support | true + |
has hardware accelerators for cryptography | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
instance of | microprocessor + |
isa | MIPS64 + |
isa family | MIPS + |
l1$ size | 80 KiB (81,920 B, 0.0781 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
ldate | May 1, 2006 + |
main image | + |
manufacturer | TSMC + |
market segment | Embedded + |
max cpu count | 1 + |
max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
max memory bandwidth | 4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) + |
max memory channels | 1 + |
microarchitecture | cnMIPS + |
model number | CN3120-550 SCP + |
name | Cavium CN3120-550 SCP + |
package | HSBGA-868 + |
part number | CN3120-550BG868-SCP + |
power dissipation | 7 W (7,000 mW, 0.00939 hp, 0.007 kW) + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
release price | $ 125.00 (€ 112.50, £ 101.25, ¥ 12,916.25) + |
series | CN3100 + |
smp max ways | 1 + |
supported memory type | DDR2-667 + |
technology | CMOS + |
thread count | 2 + |
word size | 64 bit (8 octets, 16 nibbles) + |