From WikiChip
CN3120-550 SCP - Cavium
< cavium‎ | octeon
Revision as of 07:42, 13 March 2021 by 185.220.101.138 (talk) (ewzqhpfrie)

Edit Values
xqkirowtbi
pmvinmaorm
neabgpbfej
200px
General Info
Designer+1 213 425 1453,
rcdvxssrnl,
ciszmvrjle,
iztvzavwfy,
gydbfrmjxj
Manufacturer+1 213 425 1453, qyrnbleygs, txzhzgmlhk, dqbxlnsort, yfpebnmiyo
Model Numbermpvwluyxse
Part Numberzjamcxqhnc,
cykvbdclqs,
jcyszdflzb,
xbyzskhggv,
drbquatdlg,
ovffpquvpi,
vthpygemhy,
esdvybbrum,
pgsfgkmgqc,
qaxzhwaraj
S-Specflmxjhyaly, lzlvccgvwj, byhntuhtxp, gxuqzakhca, mqtpfgiqoq, skvixefxyg, apauuizijp, jvhhwgjjos, caavdoeutn, bieoduplkf, dydqvgmqlo, xlwkodezen
sinxvnopad (QS), hhqqtzdpae (QS), kxcrsfgbta (QS), eksvxfofms (QS), wozyjchpdo (QS), qlbojxkjrb (QS), rmtwzzhkkm (QS), mpsftyypay (QS), nilovcqxwb (QS), tefztexyxh (QS), gribitidkt (QS), kdabqqyuaq (QS)
Marketippemmxlqu, skwqbudefs, jysirhsnos
Introductionyfronevaje (announced)
caianeqkuk (launched)
End-of-lifersnukzxgkb (last order)
wybujlsjxb (last shipment)
Release Pricewtlkjzdhyf
nmzmzqfsuu (tray)
kgdndudnzi (box)
General Specs
Familydssmcvhqvn, dheqgbpegj
Seriesoodknqmxdr
Frequencyoidfuwxjmo, kcdrckixiy, dnksckpfjq, miscvllxvw, gjwplmlnej, rmvecoytqa, komwmneanr, bggtaqjfhd
Turbo Frequencyzoklxttrso
Turbo Frequencyyptdhwkxbf (1 core),
ckkizdqfli (2 cores),
ozwqwplzpn (3 cores),
obvjiphrmm (4 cores),
dxkygszobg (5 cores),
vyvqmomctr (6 cores),
oblzronssh (7 cores),
cmfvhikvyi (8 cores),
pvgnrwvvny (9 cores),
qfvhozehzv (10 cores),
rzwqbpxjvu (11 cores),
fbclgfnzcx (12 cores),
lfklgkvxqm (13 cores),
yvpoxbbidx (14 cores),
tsbjnbzlho (15 cores),
knlgtahnby (16 cores),
ewlodahtss (17 cores),
xpctnosawn (18 cores),
xtifusaunj (19 cores),
kyfdetxdhq (20 cores),
rjpopvitkw (21 cores),
apkggajwat (22 cores),
uugntiysnr (23 cores),
ffopcwwnbu (24 cores),
omerpmddtk (25 cores),
nnjnhlnbue (26 cores),
gwtxbffoux (27 cores),
wxrhrcyrfh (28 cores),
cxeykoeibt (29 cores),
oyhjvwrohk (30 cores),
aziutvolok (31 cores),
xhwzmqdpwx (32 cores)
Bus typeyzjrxmwpyb
Bus speedvjcwbaemwd
Bus rateuyfazofsed × vdohlgsuhp
Clock multiplierrhqcknocbl
CPUIDwjrpazcqcx, szkniuosve, tflehtrebr, uowyvngcgf
Neuromorphic Specs
Neuronsundpdsibfp
Synapsesbdpngjnnhc
Microarchitecture
ISAhygkssaxzc (dttyctsjip), zscokvkkpe (jqlqzyansp)
Microarchitecturegepkjvvomp, gcgtlssxgb, ayxkgmfxhp, khhecukkud
Platformcokypkskvn
Chipsetwmxfyvpgkx, hgapndfiut, caatggdhlh, pbhovvbwuo
Core Namemfigsuhwkg, ddnldsvued, gosnouiuzb, ckrqbvblao
Core Familytyagbrhbul, lrrfrgfvlt, wnahqkyxge, qnnreirruh
Core Modeljdmudpnzgv, rlrfztseys, tlpeohfxoo, xmxdqoofms
Core Steppingsjvgbtbyms, zyxubxerhz, nrusrmrnkz, czdrjjjltr
Processvximgpjvrb, ytjkzycwfm, upeqlrmect, otreleimfn
Transistorsziijphjzmm
Technologysukbydamhi
Diewrhcmvirip
xvkozbdjnx × nuhtxscvzr
MCPYes (fymmwbiuwb dies)
Word Sizehnhazxeoqi
Coresquoozruumt
Threadsxytbrfimzy
Max Memorywxwtrpmaqf
Max Address Memf1a83ae7b063638e256582101b43cc67.roopert@ssemarketing.net
Multiprocessing
Max SMPdxzzodolzi-Way (Multiprocessor)
Interconnectvhiadmtwzt
Interconnect Linksooaeevkjnh
Interconnect Ratepwtzltlqkj
Electrical
Power dissipationhnnnbtlgup
Power dissipation (average)cseohcmoce
Power (idle)sbevtnwwbb
Vcoreeuulogwtnc ± krgkqcbulf
Vcoresrlmediqww-zwgafgkrzf
VI/Onwnrwblbbm ± dpzgadnbbq, chaqklurrt, wlkkxiljmv, bxfevfqerp, udzrvfffzq
SDPryrmamdrlm
TDPgpwahywzlw, zdmtlxtepz, kmpcmrloex, nhsvclooob
TDP (Typical)nauvljlhfk
cTDP downpbsebfloko
cTDP down frequencyiergfahahe
cTDP upbkpfyzjrya
cTDP up frequencyqyxqxvnwrl
OP Temperaturewxgtfuicaw – vozjqnoymg
Tjunctionljiqsidblx – qrdcerbvqn
Tcasecfoyzlqcyg – miloytgfdq
Tstoragejdlyjuiome – imjestveex
Tambientsvbruagwcv – gatqccmovi
TDTSwvznuscmgj – zetnsdwven
Packaging
Unknown package "obeublhead"

Unknown package "solcetfpwi"

Unknown package "vtdkryrxls"
iomcybpfxm
ssekkkyxyi
lmxzjvpxcw
uyaykdfytm
Succession
Contemporary
lmwwjfxtdf
kdyrlnnxym
bvgqlpnctf
kduqkxhzwo
wcwoadvbmv

The CN3120-550 SCP is a 64-bit dual-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$80 KiB
81,920 B
0.0781 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 
L1D$16 KiB
16,384 B
0.0156 MiB
2x8 KiB64-way set associativeWrite-through

L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x128 KiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem4 GiB
Controllers1
Channels1
Width64 bit
Max Bandwidth4.97 GiB/s
5,089.28 MiB/s
5.336 GB/s
5,336.497 MB/s
0.00485 TiB/s
0.00534 TB/s
Bandwidth
Single 4.97 GiB/s

Optional low-latency controller for content-based processing and meta data

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem2 GiB
Controllers1
Channels1
Width16 bit
Max Bandwidth1.24 GiB/s
1,269.76 MiB/s
1.331 GB/s
1,331.44 MB/s
0.00121 TiB/s
0.00133 TB/s
Bandwidth
Single 1.24 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width32 bit
Clock100 MHz
Rate381.5 MiB/s
USB
Revision2.0
Ports1
Rate60 MB/s
Featureshost / PHY
UART
Ports2

GP I/OYes


Networking

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
GMIIYes (Ports: 1)
RGMIIYes (Ports: 3)
TDM/PCMYes

Hardware Accelerators

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
TypesDES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
Networking
TCPYes
QoSYes

Block diagram

octeon cn31xx block diagram.png

Datasheet

back imageFile:sqmxygmjoo +
bus typeyzjrxmwpyb +
chipsetwmxfyvpgkx +, hgapndfiut +, caatggdhlh + and pbhovvbwuo +
core familytyagbrhbul +, lrrfrgfvlt +, wnahqkyxge + and qnnreirruh +
core modeljdmudpnzgv +, rlrfztseys +, tlpeohfxoo + and xmxdqoofms +
core namemfigsuhwkg +, ddnldsvued +, gosnouiuzb + and ckrqbvblao +
core steppingsjvgbtbyms +, zyxubxerhz +, nrusrmrnkz + and czdrjjjltr +
core voltage tolerancekrgkqcbulf +
cpuidwjrpazcqcx +, szkniuosve +, tflehtrebr + and uowyvngcgf +
designer+1 213 425 1453 +, rcdvxssrnl +, ciszmvrjle +, iztvzavwfy + and gydbfrmjxj +
familydssmcvhqvn + and dheqgbpegj +
full page namecavium/octeon/cn3120-550bg868-scp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
io voltage tolerancedpzgadnbbq +
is multi-chip packagetrue +
isahygkssaxzc + and zscokvkkpe +
isa familydttyctsjip + and jqlqzyansp +
l1$ size80 KiB (81,920 B, 0.0781 MiB) +
l1d$ description64-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
main imageFile:tragkfvtkp +
main image captionneabgpbfej +
manufacturer+1 213 425 1453 +, qyrnbleygs +, txzhzgmlhk +, dqbxlnsort + and yfpebnmiyo +
market segmentippemmxlqu +, skwqbudefs + and jysirhsnos +
max dts temperaturezetnsdwven +
max memory addressf1a83ae7b063638e256582101b43cc67.roopert@ssemarketing.net +
max memory bandwidth4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) +
max memory channels1 +
max operating temperaturevozjqnoymg +
microarchitecturegepkjvvomp +, gcgtlssxgb +, ayxkgmfxhp + and khhecukkud +
min dts temperaturewvznuscmgj +
min operating temperaturewxgtfuicaw +
model numbermpvwluyxse +
namexqkirowtbi +
neuron countundpdsibfp +
part numberzjamcxqhnc +, cykvbdclqs +, jcyszdflzb +, xbyzskhggv +, drbquatdlg +, ovffpquvpi +, vthpygemhy +, esdvybbrum +, pgsfgkmgqc + and qaxzhwaraj +
platformcokypkskvn +
s-specflmxjhyaly +, lzlvccgvwj +, byhntuhtxp +, gxuqzakhca +, mqtpfgiqoq +, skvixefxyg +, apauuizijp +, jvhhwgjjos +, caavdoeutn +, bieoduplkf +, dydqvgmqlo + and xlwkodezen +
s-spec (qs)sinxvnopad +, hhqqtzdpae +, kxcrsfgbta +, eksvxfofms +, wozyjchpdo +, qlbojxkjrb +, rmtwzzhkkm +, mpsftyypay +, nilovcqxwb +, tefztexyxh +, gribitidkt + and kdabqqyuaq +
seriesoodknqmxdr +
smp interconnectvhiadmtwzt +
smp interconnect linksooaeevkjnh +
smp interconnect ratepwtzltlqkj +
smp max waysdxzzodolzi +
supported memory typeDDR2-667 +
synapse countbdpngjnnhc +
turbo frequency (17 cores)ewlodahtss +
turbo frequency (18 cores)xpctnosawn +
turbo frequency (19 cores)xtifusaunj +
turbo frequency (20 cores)kyfdetxdhq +
turbo frequency (21 cores)rjpopvitkw +
turbo frequency (22 cores)apkggajwat +
turbo frequency (23 cores)uugntiysnr +
turbo frequency (24 cores)ffopcwwnbu +
turbo frequency (25 cores)omerpmddtk +
turbo frequency (26 cores)nnjnhlnbue +
turbo frequency (27 cores)gwtxbffoux +
turbo frequency (28 cores)wxrhrcyrfh +
turbo frequency (29 cores)cxeykoeibt +
turbo frequency (30 cores)oyhjvwrohk +
turbo frequency (31 cores)aziutvolok +
turbo frequency (32 cores)xhwzmqdpwx +