Semiconductor & Computer Engineering
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Core i5-520UM - Intel
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| Intel Core i5-520UM | ||||||||||
| General Info | ||||||||||
| Designer | Intel | |||||||||
| Manufacturer | Intel | |||||||||
| Model Number | i5-520UM | |||||||||
| Part Number | CN80617005352AA | |||||||||
| S-Spec | SLBQP, SLBSQ | |||||||||
| Market | Mobile | |||||||||
| Introduction | January 7, 2010 (announced) January 7, 2010 (launched) | |||||||||
| Release Price | $241 | |||||||||
| Shop | Amazon | |||||||||
| General Specs | ||||||||||
| Family | Core i5 | |||||||||
| Series | i5-500 | |||||||||
| Locked | Yes | |||||||||
| Frequency | 1,066.66 MHz | |||||||||
| Turbo Frequency | Yes | |||||||||
| Turbo Frequency | 1,866.66 MHz (1 core), 1,599.99 MHz (2 cores) | |||||||||
| Bus type | DMI 1.0 | |||||||||
| Bus rate | 1 × 2.5 GT/s | |||||||||
| Clock multiplier | 8 | |||||||||
| CPUID | 0x20655 | |||||||||
| Microarchitecture | ||||||||||
| ISA | x86-64 (x86) | |||||||||
| Microarchitecture | Westmere | |||||||||
| Platform | Calpella | |||||||||
| Chipset | Ibex Peak | |||||||||
| Core Name | Arrandale | |||||||||
| Core Family | 6 | |||||||||
| Core Model | 37 | |||||||||
| Core Stepping | K0, C2 | |||||||||
| Process | 32 nm | |||||||||
| Transistors | 382,000,000 | |||||||||
| Technology | CMOS | |||||||||
| Die | 81 mm² | |||||||||
| Word Size | 64 bit | |||||||||
| Cores | 2 | |||||||||
| Threads | 4 | |||||||||
| Max Memory | 8 GiB | |||||||||
| Multiprocessing | ||||||||||
| Max SMP | 1-Way (Uniprocessor) | |||||||||
| Electrical | ||||||||||
| TDP | 18 W | |||||||||
| Tjunction | 0 °C – 105 °C | |||||||||
| Tstorage | -25 °C – 125 °C | |||||||||
| Packaging | ||||||||||
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Core i5-520UM is a 64-bit x86 dual-core mobile microprocessor introduced by Intel in 2010. This processor, which is based on the Westmere microarchitecture (Arrandale core), is manufactured on a 32 nm process. This MPU operates at a base frequency of 1.07 GHz with a Turbo Boost frequency of 1.87 GHz and a TDP of 18 W. This processor incorporated the HD Graphics (Ironlake) IGP on the same package operating at a base frequency of 166.00 MHz and a burst frequency of 500.00 MHz.
Cache
- Main article: Westmere § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
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Integrated Graphics Information
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Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Core i5-520UM - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-520UM - Intel#io + |
| device id | 0x0046 + |
| has ecc memory support | false + |
| has extended page tables support | true + |
| has feature | Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 1.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Flex Memory Access + |
| has intel enhanced speedstep technology | true + |
| has intel flex memory access support | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 1 0 | true + |
| has intel vpro technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| integrated gpu | HD Graphics (Ironlake) + |
| integrated gpu base frequency | 166 MHz (0.166 GHz, 166,000 KHz) + |
| integrated gpu designer | Intel + |
| integrated gpu execution units | 12 + |
| integrated gpu max frequency | 500 MHz (0.5 GHz, 500,000 KHz) + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | 12-way set associative + |
| l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| supported memory type | DDR3-800 + |