Template:mpu Celeron G3900E is a 64-bit dual-core x86 budget mobile microprocessor introduced by Intel in late 2015. This processor, which is based on the Skylake microarchitecture and is manufactured on a 14 nm process, has a base frequency of 2.4 GHz with a TDP of 35 W. This processor incorporates the HD Graphics 510 GPU clocked at 350 MHz with a max frequency of 950 MHz.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative write-back L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB 4-way set associative write-back L3$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     2x1 MiB   write-back