Template:mpu The Intel Xeon E3-1284L v3 is a quad core 64-bit server microprocessor released by Intel in 2014. The microprocessor is based on the Haswell microarchitecture. This MPU includes the Intel Iris Pro 5200 integrated graphic and features the 128 MB L4$ Crystal Well cache.

Cache

Main article: Haswell § Cache

This specific microprocessor includes the Crystal Well cache.

Cache Info [Edit Values]
L1I$	128 KiB 131,072 B 0.125 MiB	4x32 KiB 8-way set associative (per core, write-back)
L1D$	128 KiB 131,072 B 0.125 MiB	4x32 KiB 8-way set associative (per core, write-back)
L2$	1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB	4x256 KiB 8-way set associative (per core, write-back)
L3$	6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB	12-way set associative (shared)
L4$	128 MiB 131,072 KiB 134,217,728 B 0.125 GiB	16-way set associative (see Crystal Well)

Graphics

Integrated Graphic Information
GPU	Intel Iris Pro Graphics 5200
Displays	3
Frequency	200 MHz 0.2 GHz 200,000 KHz
Max frequency	750 MHz 0.75 GHz 750,000 KHz
Max memory	1 GiB 1,024 MiB 1,048,576 KiB 1,073,741,824 B
Output	DisplayPort, Embedded DisplayPort, HDMI, VGA

Memory controller

Integrated Memory Controller
Type	DDR3L-1333, DDR3L-1600
Controllers	1
Channels	2
ECC Support	Yes
Max bandwidth	25,600 MB/s
Max memory	32,768 MB

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions F16C 16-bit Floating Point Conversion NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology TXT Trusted Execution Technology (SMX) TSX Transactional Synchronization Extensions