Template:mpu The Xeon D-1557 is a 64-bit dodeca-core x86-64 microserver SoC that was introduced by Intel in February of 2016. The D-1557 operates at 1.5 GHz with a turbo frequency of 2.1 GHz. This chip, which is based on the Broadwell microarchitecture and manufactured in 14 nm process, has a TDP of 45 W and can support up to 128 GB of RAM (DDR3L/DDR4).

Cache

Main article: Broadwell § Cache

Cache Info [Edit Values]
L1I$	384 KiB 393,216 B 0.375 MiB	12x32 KiB 8-way set associative (per core)
L1D$	384 KiB 393,216 B 0.375 MiB	12x32 KiB 8-way set associative (per core)
L2$	3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB	12x256 KiB 8-way set associative (per core)
L3$	18 MiB 18,432 KiB 18,874,368 B 0.0176 GiB	12x1.5 MiB (per core)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type	DDR3L-1333, DDR3L-1600, DDR4-1600, DDR4-1867, DDR4-2133
Controllers	1
Channels	2
ECC Support	Yes
Max memory	128 GiB

Networking

Networking
SFI interface	Yes
KR interface	Yes
KR4 interface	No
KX interface	Yes
KX4 interface	No
10Base-T	No
100Base-T	No
1000Base-T	Yes
10GBase-T	Yes

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions F16C 16-bit Floating Point Conversion NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology TXT Trusted Execution Technology (SMX) TSX Transactional Synchronization Extensions