Template:mpu i486DX4-100 was a fourth-generation x86 microprocessor introduced by Intel in 1994. This chip, which is based on the 80486 microarchitecture, had a clock multiplier of x2, x2.5, and x3 with a max operating frequency of 100 MHz, three times the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM). The DX4 series had twice as much cache space as the older processors.

Cache

Main article: 80486 § Cache

The i486dx4-100 was offered with two cache policies. Models that came with a write-back cache were marked by an "&EW" identifier. Models that came with a write-through policy were marked by "&E".

Cache Info [Edit Values]
L1$	16 KiB 16,384 B 0.0156 MiB	1x16 KiB 4-way set associative (unified, write-through/write-back policy)

Graphics

This chip had no integrated graphics processing unit.

Features

• System Management Mode (SMM)

Gallery

• 

  A80486DX4100, S-Spec SK096

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  A80486DX4100, S-Spec SK096

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  A80486DX4100, S-Spec SK096

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  A80486DX4100, S-Spec SK051

• 

  A80486DX4100, S-Spec SK051

See also

• 80486 family