Template:mpu The CN3860-500 NSP is a 64-bit hexadeca-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2005. This processor, which incorporates sixteen cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.