Template:mpu The CN3850-500 EXP is a 64-bit dodeca-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates twelve cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.