Template:mpu The CN3630-400 SCP is a 64-bit quad-core MIPS secure network communication microprocessor (SNP) designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and encryption. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

Cache

Main article: cnMIPS § Cache

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Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 160 KiB 163,840 B 0.156 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 64-way set associative   L1D$ 32 KiB 32,768 B 0.0313 MiB 4x8 KiB 64-way set associative Write-through L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     1x512 KiB 8-way set associative

Memory controller

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	Integrated Memory Controller
	Max Type DDR2-800 Supports ECC Yes Max Mem 16 GiB Controllers 1 Channels 1 Width 64 bit Max Bandwidth 5.96 GiB/s 6,103.04 MiB/s 6.4 GB/s 6,399.501 MB/s 0.00582 TiB/s 0.0064 TB/s Bandwidth Single 5.96 GiB/s

Expansions

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	Expansion Options
	PCI-X Width 64 bit Clock 133.33 MHz Rate 1,017.25 MiB/s Features host or slave UART Ports 2 GP I/O Yes

Networking

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	Networking
	MII RGMII Yes (Ports: 8) SPI SPI-4.2 Yes (Ports: 2)

Hardware Accelerators

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	Hardware Accelerators
	Encryption Hardware Implementation Yes Types DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH Networking TCP Yes QoS Yes

Block diagram

Datasheet

• OCTEON CN38XX /CN36XX 4 to 16-Core Product Brief