Difference between revisions of "intel/xeon e7/e7-4807"

	Edit Values
	Xeon E7-4807
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	E7-4807
Part Number	AT80615006432AB
S-Spec	SLC3L
Market	Server
Introduction	April 5, 2011 (announced); April 5, 2011 (launched)
End-of-life	August 21, 2015 (last order); February 5, 2016 (last shipment)
Release Price	$890.00
Shop	Amazon
	General Specs
Family	Xeon E7
Series	E7-4800
Locked	Yes
Frequency	1,866.66 MHz
Bus type	QPI
Bus rate	4.80 GT/s
Clock multiplier	14
CPUID	206F2
	Microarchitecture
Microarchitecture	Westmere
Platform	Boxboro
Chipset	Boxboro
Core Name	Westmere EX
Core Family	6
Core Model	47
Core Stepping	A2
Process	32 nm
Transistors	2,600,000,000
Technology	CMOS
Die	513 mm²
Word Size	64 bit
Cores	6
Threads	12
Max Memory	2 TiB
	Multiprocessing
Max SMP	4-Way (Multiprocessor)
	Electrical
Vcore	1.35 V
TDP	95 W
Tcase	5 °C – 70 °C
Tstorage	-40 °C – 85 °C
	Packaging
Dimension	49.1 mm x 56.4 mm x 4.2 mm
Pitch	1 mm
Pin Count	1567
Socket	LGA-1567

Latest revision as of 15:28, 13 December 2017

Xeon E7-4807 is a 64-bit hexa-core x86 data center microprocessor that supports up to 4 sockets. This first generation (Westmere-based) Xeon E7 processor operates at 1.86 GHz with 95 W TDP but does not support turbo boost technology. This processor supports up to 4 channels of DDR3, supporting up to 2 TB of memory.

Cache[edit]

Main article: Westmere § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

384 KiB

393,216 B
0.375 MiB

L1I$	192 KiB 196,608 B 0.188 MiB	6x32 KiB	4-way set associative	write-back
L1D$	192 KiB 196,608 B 0.188 MiB	6x32 KiB	8-way set associative	write-back

L2$

1.5 MiB

1,536 KiB
1,572,864 B
0.00146 GiB

		6x256 KiB	8-way set associative	write-back

L3$

18 MiB

18,432 KiB
18,874,368 B
0.0176 GiB

		6x3 MiB	16-way set associative	write-back

Graphics[edit]

This SoC has no integrated graphics processing unit.

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR3-800
Supports ECC	Yes
Max Mem	2 TiB
Controllers	1
Channels	4
Max Bandwidth	23.84 GiB/s 24,412.16 MiB/s 25.598 GB/s 25,598.005 MB/s 0.0233 TiB/s 0.0256 TB/s
Bandwidth	Single 5.96 GiB/s Double 11.92 GiB/s Triple 17.88 GiB/s Quad 23.84 GiB/s

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AES	AES Encryption Instructions

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
EIST	Enhanced SpeedStep Technology
TXT	Trusted Execution Technology (SMX)
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)

@@ Line 1: / Line 1: @@
 {{intel title|Xeon E7-4807}}
-{{mpu
+{{chip
 | name                = Xeon E7-4807
 | no image            = Yes

has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d + and Extended Page Tables +
has intel enhanced speedstep technology	true +
has intel trusted execution technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
l1$ size	384 KiB (393,216 B, 0.375 MiB) +
l1d$ description	8-way set associative +
l1d$ size	192 KiB (196,608 B, 0.188 MiB) +
l1i$ description	4-way set associative +
l1i$ size	192 KiB (196,608 B, 0.188 MiB) +
l2$ description	8-way set associative +
l2$ size	1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l3$ description	16-way set associative +
l3$ size	18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +
max memory bandwidth	23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) +
max memory channels	4 +
supported memory type	DDR3-800 +

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