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Latest revision as of 15:27, 13 December 2017

Edit Values
Xeon E5-2609 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-2609 v4
Part NumberCM8066002032901,
BX80660E52609V4
S-SpecSR2P1
QKEW (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$306.00
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-2000
LockedYes
Frequency1,700 MHz
Bus typeQPI
Bus speed3,200 MHz
Bus rate2 × 6.4 GT/s
Clock multiplier17
CPUID406F1
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureBroadwell
PlatformGrantley EP 2S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingR0
Process14 nm
Transistors3,200,000,000
TechnologyCMOS
Die246.24 mm²
Word Size64 bit
Cores8
Threads8
Max Memory1,536 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP85 W
Tcase0 °C – 74 °C
Tstorage-25 °C – 125 °C

The Xeon E5-2609 v4 is a 64-bit octa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for basic 2S environments (1U square form factor). Operating at 1.7 GHz with a turbo boost frequency of 3.2 GHz for a single active core, this MPU has a TDP of 85 W and is manufactured on a 14 nm process (based on Broadwell). This specific model has no hyper-threading support.

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core, write-back)
L1D$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core, write-back)
L2$ 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
8x256 KiB 8-way set associative (per core, write-back)
L3$ 20 MiB
20,480 KiB
20,971,520 B
0.0195 GiB
8x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-1866
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 55.63 GiB/s
Bandwidth (single) 13.91 GiB/s
Bandwidth (dual) 27.82 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2609_v4&oldid=70980"
Facts about "Xeon E5-2609 v4 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-2609 v4 - Intel#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel vpro technologytrue +
has second level address translation supporttrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ description20-way set associative +
l3$ size20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
max pcie lanes40 +