Semiconductor & Computer Engineering
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Difference between revisions of "intel/xeon e5/e5-2628l v4"
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Revision as of 14:55, 13 December 2017
Template:mpu The Xeon E5-2628L v4 is a 64-bit dodeca-core x86 microprocessor introduced by Intel in 2016. This embedded server MPU is designed for low-power 2S environments. Operating at 1.9 GHz with a turbo boost frequency of 2.4 GHz for a single active core, this MPU has a TDP of 75 W and is manufactured on a 14 nm process (based on Broadwell).
Cache
- Main article: Broadwell § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 384 KiB 393,216 B 0.375 MiB |
12x32 KiB 8-way set associative (per core, write-back) |
| L1D$ | 384 KiB 393,216 B 0.375 MiB |
12x32 KiB 8-way set associative (per core, write-back) |
| L2$ | 3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB |
12x256 KiB 8-way set associative (per core, write-back) |
| L3$ | 30 MiB 30,720 KiB 31,457,280 B 0.0293 GiB |
12x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics
This microprocessor has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR4-2133 |
| Controllers | 1 |
| Channels | 4 |
| ECC Support | Yes |
| Max bandwidth | 63.58 GiB/s |
| Bandwidth (single) | 15.89 GiB/s |
| Bandwidth (dual) | 31.79 GiB/s |
| Max memory | 1,536 GiB |
| Physical Address Extensions | 46 bit |
Expansions
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Expansion Options
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Features
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Supported x86 Extensions & Processor Features
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Facts about "Xeon E5-2628L v4 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E5-2628L v4 - Intel#io + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions + |
| has intel enhanced speedstep technology | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 2 0 | true + |
| has intel vpro technology | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
| l3$ description | 20-way set associative + |
| l3$ size | 30 MiB (30,720 KiB, 31,457,280 B, 0.0293 GiB) + |
| max pcie lanes | 40 + |