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Difference between revisions of "intel/pentium (2009)/n4200"
< intel‎ | pentium (2009)

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== Expansions ==
 
== Expansions ==
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{{expansions
 
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| pcie revision      = 2.0
 
| pcie lanes        = 6
 
| pcie lanes        = 6

Revision as of 14:54, 13 December 2017

Template:mpu Pentium N4200 is a quad-core 64-bit x86 mobile microprocessor introduced by Intel in 2016. The processor is based on Goldmont microarchitecture and is manufactured on a 14 nm process. The chip operates at 1.1 GHz with burst frequency of 2.5 GHz and has a TDP of 6 W (SDP of 4 W). This MPU incorporates Intel's HD Graphics 505 GPU operating at 200 MHz with a burst frequency of 750 MHz.

Cache

Main article: Goldmont's Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core)
L1D$ 96 KiB
98,304 B
0.0938 MiB
4x24 KiB 6-way set associative (per core)
L2$ 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
2x1 MiB 16-way set associative (per 2 cores)
L3$ 0 KiB
0 MiB
0 B
0 GiB
No L3$

Memory controller

Integrated Memory Controller
Type LPDDR3-1333, LPDDR3-1600, LPDDR3-2400, DDR3L-1333, DDR3L-1600, DDR3L-1867, LPDDR4-1600, LPDDR4-2133, LPDDR4-2400
Controllers 1
Channels 2
ECC Support No
Bandwidth (single) 19,200 MB/s
Bandwidth (dual) 38,400 MB/s
Max memory 8,192 MB

Graphics

Integrated Graphic Information
GPU HD Graphics 505
Device ID 0x5A84
Execution Units 18
Displays 3
Frequency 200 MHz
0.2 GHz
200,000 KHz
Max frequency 750 MHz
0.75 GHz
750,000 KHz
Max memory 8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
Output DisplayPort, Embedded DisplayPort, HDMI, DSI
DirectX 12
OpenGL 4.3
OpenCL 1.2
OpenGL ES 3.0
HDMI 1.4b
DP 1.2
eDP 1.3
Max HDMI Res 3840x2160 @30 Hz
Max DSI Res 2560x1600 @60 Hz
Max DP Res 4096x2160 @60 Hz
Max eDP Res 3840x2160 @60 Hz
Intel Quick Sync Video
Intel Clear Video
  • Video decode hardware acceleration including support for HEVC (H.265), H.264, MVC, VP8, VP9, MPEG2, VC-1, WMV9, JPEG/MJPEG.
  • Video encode hardware acceleration including support for HEVC (H.265), H.264, MVC, VP8, VP9, JPEG/MJPEG.

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes6
Configs4x1, 2x1 + 1x2 + 1x2
USB
Revision2.0, 3.0
Ports8
UART
SATA
Revision3.0
Ports3

GP I/OYes


  • 2x USB 2.0 ports
  • 6x USB 3.0 ports
    • 1x USB Dual Role
    • 1x Dedicated Port
    • 3x multiplexed with PCIe 2.0
    • 1x multiplexed with SATA 3.0

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
AESAES Encryption Instructions
NXNo-eXecute
BPTBurst Performance Technology
EISTEnhanced SpeedStep Technology
TXTTrusted Execution Technology (SMX)
EPTExtended Page Tables (SLAT)
Facts about "Pentium N4200 - Intel"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Pentium N4200 - Intel#io +
device id0x5A84 +
has extended page tables supporttrue +
has featureintegrated gpu +, Advanced Encryption Standard Instruction Set Extension +, Burst Performance Technology +, Enhanced SpeedStep Technology +, Trusted Execution Technology + and Extended Page Tables +
has intel burst performance technologytrue +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has second level address translation supporttrue +
has x86 advanced encryption standard instruction set extensiontrue +
integrated gpuHD Graphics 505 +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu max frequency750 MHz (0.75 GHz, 750,000 KHz) +
integrated gpu max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB) +
l1d$ description6-way set associative +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ descriptionNo L3$ +
l3$ size0 MiB (0 KiB, 0 B, 0 GiB) +
max pcie lanes6 +