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Difference between revisions of "intel/xeon e5/e5-2673 v4"
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Revision as of 15:48, 13 December 2017
Template:mpu The Xeon E5-2673 v4 is a 64-bit icosa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for 2S environments. Operating at 2.3 GHz with a turbo boost frequency of ? GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a 14 nm process (based on Broadwell).
Cache
- Main article: Broadwell § Cache
Cache Info [Edit Values] | ||
L1I$ | 640 KiB 655,360 B 0.625 MiB |
20x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 640 KiB 655,360 B 0.625 MiB |
20x32 KiB 8-way set associative (per core, write-back) |
L2$ | 5 MiB 5,120 KiB 5,242,880 B 0.00488 GiB |
20x256 KiB 8-way set associative (per core, write-back) |
L3$ | 50 MiB 51,200 KiB 52,428,800 B 0.0488 GiB |
20x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics
This microprocessor has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller | |
Type | DDR4-2400 |
Controllers | 1 |
Channels | 4 |
ECC Support | Yes |
Max bandwidth | 71.53 GiB/s |
Bandwidth (single) | 17.88 GiB/s |
Bandwidth (dual) | 35.76 GiB/s |
Max memory | 1,536 GiB |
Physical Address Extensions | 46 bit |
Expansions
Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Xeon E5-2673 v4 - Intel"
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1d$ description | 8-way set associative + |
l1d$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 5 MiB (5,120 KiB, 5,242,880 B, 0.00488 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 50 MiB (51,200 KiB, 52,428,800 B, 0.0488 GiB) + |