From WikiChip
Difference between revisions of "amd/ryzen threadripper/1950x"
(→Memory controller: JEDEC DDR4 "B" Spec from June 2017 defines 2666 and 3200 rates. They are not "overclocking" or non-spec.) |
|||
Line 93: | Line 93: | ||
}} | }} | ||
* eMMC, LPC, SMBus, SPI/eSPI | * eMMC, LPC, SMBus, SPI/eSPI | ||
− | |||
− | |||
− | |||
== Graphics == | == Graphics == |
Revision as of 11:38, 31 August 2017
Template:mpu Ryzen Threadripper 1950X is a 64-bit hexadeca-core high-performance x86 desktop microprocessor set to be introduced by AMD in mid-2017. The 1950X, which is based on their Zen microarchitecture, is fabricated on a 14 nm process. The 1950X operates at a base frequency of 3.4 GHz with a with a TDP of 180 W and a Boost frequency of 4.0 GHz. This MPU supports up to 1 TiB of quad-channel DDR4-2666 ECC memory.
Cache
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller
This CPU supports 8 DIMMs of rates 1,333 MT/s - 3,200 MT/s (UDIMM/SODIMM).
Integrated Memory Controller
|
||||||||||||||
|
Expansions
This processor includes 60 PCIe lanes with PHY of 16 lanes may each have a maximum of 8 PCIe ports (x1, x2, x4, x8, x16).
Expansion Options
|
||||||||
|
- eMMC, LPC, SMBus, SPI/eSPI
Graphics
This processor has no integrated graphics.
Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
- This model has full XFR support, allowing for an additional +200 MHz0.2 GHzboost frequency.
200,000 kHz
Facts about "Ryzen Threadripper 1950X - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Ryzen Threadripper 1950X - AMD#io + |
amd xfr headroom | 200 MHz (0.2 GHz, 200,000 kHz) + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd extended frequency range | true + |
has amd sensemi technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Extended Frequency Range + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |
max memory bandwidth | 79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) + |
max memory channels | 4 + |
max pcie lanes | 60 + |
supported memory type | DDR4-2666 + |