Line 120: | Line 120: | ||
|avx=Yes | |avx=Yes | ||
|avx2=Yes | |avx2=Yes | ||
− | + | |avx512f=No | |
+ | |avx512cd=No | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=No | ||
+ | |avx512dq=No | ||
+ | |avx512vl=No | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No | ||
Line 142: | Line 153: | ||
|flex=No | |flex=No | ||
|fastmem=No | |fastmem=No | ||
+ | |ivmd=No | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
|isrt=No | |isrt=No | ||
|sba=No | |sba=No | ||
Line 165: | Line 183: | ||
|amdvi=Yes | |amdvi=Yes | ||
|amdv=Yes | |amdv=Yes | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
|rvi=No | |rvi=No | ||
|smt=Yes | |smt=Yes | ||
|sensemi=Yes | |sensemi=Yes | ||
− | |xfr= | + | |xfr=Yes |
}} | }} | ||
* This model has full {{amd|XFR}} support, allowing for an additional +200 MHz boost frequency. | * This model has full {{amd|XFR}} support, allowing for an additional +200 MHz boost frequency. |
Revision as of 08:25, 27 July 2017
Template:mpu Ryzen 3 1300X is a 64-bit quad-core entry-level performance x86 desktop microprocessor introduced by AMD in late 2017. This processor is based on AMD's Zen microarchitecture and is fabricated on a 14 nm process. The 1300X operates at a base frequency of 3.4 GHz with a TDP of 65 W and a Boost frequency of 3.7 GHz. This MPU supports up to 64 GiB of dual-channel DDR4-2666 ECC memory.
Cache
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
This processor incorporates 2 DDR4 PHYs, each supporting 1 channel of 64-bit data plus ECC with 2 DIMMs per channel. DIMMs of rates 1,333 MT/s - 3,200 MT/s are supported (UDIMM/SODIMM). Note that despite AMD's support for memory rates of 3,200 MT/s and possibly higher, rates beyond 2666 MT/s exceeds the JEDEC specification and is thus considered overclocking which voids AMD product warranty and likely any vendor or retailer warranties as well.
Integrated Memory Controller
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[Edit] Memory Configurations | |||
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Dual Channel | Single Rank | 2 DIMMs | DDR4-2666 |
4 DIMMs | DDR4-2133 | ||
Double Rank | 2 DIMMs | DDR4-2400 | |
4 DIMMs | DDR4-1866 |
Expansions
The 1300 includes 20 PCIe lanes - 16 for a DGP and 4 for storage (NVMe or 2 ports SATA Express).
Expansion Options
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- eMMC, LPC, SMBus, SPI/eSPI
Audio
Support Azalia High Definition Audio
Graphics
This processor has no integrated graphics.
Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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- This model has full XFR support, allowing for an additional +200 MHz boost frequency.
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Ryzen 3 1300X - AMD#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd extended frequency range | true + |
has amd sensemi technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Extended Frequency Range + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
max memory bandwidth | 39.74 GiB/s (40,693.76 MiB/s, 42.671 GB/s, 42,670.5 MB/s, 0.0388 TiB/s, 0.0427 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 20 + |
supported memory type | DDR4-2666 + |