From WikiChip
Difference between revisions of "renesas/r-car/h3"
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|technology=CMOS | |technology=CMOS | ||
|word size=64 bit | |word size=64 bit | ||
− | |core count= | + | |core count=10 |
− | |thread count= | + | |thread count=10 |
|max cpus=1 | |max cpus=1 | ||
|v core=0.8 V | |v core=0.8 V | ||
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|package module 1={{packages/renesas/fcbga-1384}} | |package module 1={{packages/renesas/fcbga-1384}} | ||
}} | }} | ||
− | '''R-Car H3''' is a {{arch|64}} [[ | + | '''R-Car H3''' is a {{arch|64}} [[deca-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and two {{armh|Cortex-R7}} cores for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the [[imagination technologies|Imagination]]'s {{imgtec|PowerVR GX6650}} [[GPU]]. |
Samples for the H3 were available starting December 2015 with Renesas expecting mass production to begin in March 2018 and reach a volume of 100,000 units per month in March 2019. | Samples for the H3 were available starting December 2015 with Renesas expecting mass production to begin in March 2018 and reach a volume of 100,000 units per month in March 2019. | ||
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{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A57 § Cache}} | {{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A57 § Cache}} | ||
{{cache size | {{cache size | ||
− | |l1 cache= | + | |l1 cache=704 KiB |
− | |l1i cache= | + | |l1i cache=384 KiB |
− | |l1i break=4x48+ | + | |l1i break=4x48+6x32 KiB |
− | |l1d cache= | + | |l1d cache=320 KiB |
− | |l1d break= | + | |l1d break=10x32 KiB |
|l2 cache=2.5 MiB | |l2 cache=2.5 MiB | ||
}} | }} |
Revision as of 06:55, 23 July 2017
Template:mpu R-Car H3 is a 64-bit deca-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The H3 incorporates four Cortex-A57 cores, four Cortex-A53 cores, and two Cortex-R7 cores for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the Imagination's PowerVR GX6650 GPU.
Samples for the H3 were available starting December 2015 with Renesas expecting mass production to begin in March 2018 and reach a volume of 100,000 units per month in March 2019.
Cache
- Main articles: Cortex-A53 § Cache and Cortex-A57 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
- PCI Express2.0 (1 lane) x 2 ch
- USB 3.0 Host interface (DRD) × 1 ports (wPHY)
- USB 2.0 Host/Function/OTG interface × 2 ports (wPHY)
- SD Host interface × 4 ch (SDR104)
- Multimedia card interface × 2 ch
- Serial ATA interface × 1 ch
- Media local bus (MLB) Interface × 1 ch (3 pin interface)
- Controller Area Network (CAN-FD support) Interface × 2ch
- Ethernet AVB 1.0-compatible MAC built in Interface: RGMII / Ethernet AVB (802.1BA)
- SYS-DMAC x 48 ch, Realtime-DMAC x 16 ch,
- Audio-DMAC x 32 ch, Audio(peripheral)-DMAC x 29 ch
- 32bit timer x 26 ch
- PWM timer × 7 ch
- I2C bus interface × 7 ch
- Serial communication interface (SCIF) × 11 ch
- Quad serial peripheral interface (QSPI) x 2 ch (for boot, HyperFlash support)
- Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
- Ethernet controller (IEEE802.3u, RMII, without PHY)
- Digital radio interface (DRIF) × 4 ch
Graphics
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Integrated Graphics Information
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Features
[Edit/Modify Supported Features]
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Supported ARM Extensions & Processor Features
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Block Diagram
Facts about "R-Car H3 - Renesas"
has ecc memory support | false + |
integrated gpu | PowerVR GX6650 + |
integrated gpu designer | Imagination Technologies + |
l1$ size | 704 KiB (720,896 B, 0.688 MiB) + |
l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ size | 2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) + |
max memory bandwidth | 47.68 GiB/s (48,824.32 MiB/s, 51.196 GB/s, 51,196.01 MB/s, 0.0466 TiB/s, 0.0512 TB/s) + |
max memory channels | 4 + |
supported memory type | LPDDR4-3200 + |