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Difference between revisions of "renesas/r-car/h3"
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'''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a single {{armh|Cortex-R7}} core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. | '''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a single {{armh|Cortex-R7}} core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A57 § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=640 KiB | ||
+ | |l1i cache=352 KiB | ||
+ | |l1i break=4x48+5x32 KiB | ||
+ | |l1d cache=288 KiB | ||
+ | |l1d break=9x32 KiB | ||
+ | |l2 cache=2.5 MiB | ||
+ | }} |
Revision as of 04:49, 23 July 2017
Template:mpu R-Car H3 is a 64-bit nona-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The H3 incorporates four Cortex-A57 cores, four Cortex-A53 cores, and a single Cortex-R7 core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory.
Cache
- Main articles: Cortex-A53 § Cache and Cortex-A57 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "R-Car H3 - Renesas"
has ecc memory support | false + |
integrated gpu | PowerVR GX6650 + |
integrated gpu designer | Imagination Technologies + |
l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1d$ size | 288 KiB (294,912 B, 0.281 MiB) + |
l1i$ size | 352 KiB (360,448 B, 0.344 MiB) + |
l2$ size | 2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) + |
max memory bandwidth | 47.68 GiB/s (48,824.32 MiB/s, 51.196 GB/s, 51,196.01 MB/s, 0.0466 TiB/s, 0.0512 TB/s) + |
max memory channels | 4 + |
supported memory type | LPDDR4-3200 + |