From WikiChip
Difference between revisions of "renesas/r-car/v2h"
Line 29: | Line 29: | ||
}} | }} | ||
'''R-Car V2H''' is high-performance embedded {{arch|64}} [[dual-core]] [[arm]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2014. The V2H has two {{armh|Cortex-A15}} cores operating at 1 GHz and incorporates the [[imagination technologies|Imagination]] {{imgtec|PowerVR SGX531}} [[GPU]]. This SoC supports up to DDR3-1600 memory. | '''R-Car V2H''' is high-performance embedded {{arch|64}} [[dual-core]] [[arm]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2014. The V2H has two {{armh|Cortex-A15}} cores operating at 1 GHz and incorporates the [[imagination technologies|Imagination]] {{imgtec|PowerVR SGX531}} [[GPU]]. This SoC supports up to DDR3-1600 memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|arm holdings/microarchitectures/cortex-a15#Memory_Hierarchy|l1=Cortex-A15 § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=128 KiB | ||
+ | |l1i cache=64 KiB | ||
+ | |l1i break=2x32 KiB | ||
+ | |l1d cache=64 KiB | ||
+ | |l1d break=2x32 KiB | ||
+ | |l2 cache=1 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR3-1600 | ||
+ | |ecc=No | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=32 bit | ||
+ | |max bandwidth=5.96 GiB/s | ||
+ | |bandwidth schan=5.96 GiB/s | ||
+ | }} |
Revision as of 03:44, 23 July 2017
Template:mpu R-Car V2H is high-performance embedded 64-bit dual-core arm SoC designed by Renesas for the automotive industry and introduced in 2014. The V2H has two Cortex-A15 cores operating at 1 GHz and incorporates the Imagination PowerVR SGX531 GPU. This SoC supports up to DDR3-1600 memory.
Cache
- Main article: Cortex-A15 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||||
|
Facts about "R-Car V2H - Renesas"
has ecc memory support | false + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
max memory bandwidth | 5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR3-1600 + |