From WikiChip
Difference between revisions of "renesas/r-car/m3"
< renesas‎ | r-car

Line 18: Line 18:
 
|microarch=Cortex-A53
 
|microarch=Cortex-A53
 
|microarch 2=Cortex-A57
 
|microarch 2=Cortex-A57
 +
|microarch 3=Cortex-R7
 
|core name=Cortex-A53
 
|core name=Cortex-A53
 
|core name 2=Cortex-A57
 
|core name 2=Cortex-A57
 +
|core name 3=Cortex-R7
 
|process=16 nm
 
|process=16 nm
 
|technology=CMOS
 
|technology=CMOS

Revision as of 03:23, 23 July 2017

Template:mpu R-Car M3 is a 64-bit hepta-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The M3 incorporates four Cortex-A53 cores, two Cortex-A57, and an additional Cortex-R7 core for real-time processing. This chip supports up to dual-channel LPDDR4-3200 memory.

Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/m3&oldid=56037"