From WikiChip
Difference between revisions of "intel/xeon e3/e3-1270 v5"
< intel

Line 75: Line 75:
 
== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=DDR3L-1600  
+
|type=DDR3L-1600
 
|type 2=DDR4-2133
 
|type 2=DDR4-2133
 
|ecc=Yes
 
|ecc=Yes
Line 81: Line 81:
 
|controllers=1
 
|controllers=1
 
|channels=2
 
|channels=2
−
|max bandwidth=35.76 GiB/s
+
|max bandwidth=31.79 GiB/s
−
|bandwidth schan=17.88 GiB/s
+
|bandwidth schan=15.89 GiB/s
−
|bandwidth dchan=35.76 GiB/s
+
|bandwidth dchan=31.79 GiB/s
 
}}
 
}}
  
Line 98: Line 98:
 
This chip has no integrated graphics processing unit.
 
This chip has no integrated graphics processing unit.
  
−
== Features ==  
+
== Features ==
 
{{x86 features
 
{{x86 features
 
|real=Yes
 
|real=Yes
Line 138: Line 138:
 
|bpt=No
 
|bpt=No
 
|eist=Yes
 
|eist=Yes
−
|sst=Yes
+
|sst=No
 
|flex=No
 
|flex=No
 
|fastmem=No
 
|fastmem=No
Line 147: Line 147:
 
|att=No
 
|att=No
 
|ipt=No
 
|ipt=No
−
|tsx=Yes
+
|tsx=No
−
|txt=Yes
+
|txt=No
−
|ht=Yes
+
|ht=No
−
|vpro=Yes
+
|vpro=No
 
|vtx=Yes
 
|vtx=Yes
 
|vtd=Yes
 
|vtd=Yes
 
|ept=Yes
 
|ept=Yes
−
|mpx=Yes
+
|mpx=No
 
|sgx=Yes
 
|sgx=Yes
 
|securekey=Yes
 
|securekey=Yes
−
|osguard=Yes
+
|osguard=No
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
Line 164: Line 164:
 
|amdvi=No
 
|amdvi=No
 
|amdv=No
 
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 
|rvi=No
 
|rvi=No
 
|smt=No
 
|smt=No

Revision as of 15:22, 8 July 2017

Template:mpu Xeon E3-1270 v5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 3.6 GHz with turbo boost of 4 GHz. The E3-1270 V5 has a TDP of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no integrated graphics processor.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB4-way set associativewrite-back
L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiB write-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3L-1600, DDR4-2133
Supports ECCYes
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes16
Configs1x16, 2x8, 1x8+2x4


Graphics

This chip has no integrated graphics processing unit.

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
EISTEnhanced SpeedStep Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e3/e3-1270_v5&oldid=53259"
Facts about "Xeon E3-1270 v5 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E3-1270 v5 - Intel#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Software Guard Extensions + and Secure Key Technology +
has intel enhanced speedstep technologytrue +
has intel secure key technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max pcie lanes16 +
supported memory typeDDR3L-1600 + and DDR4-2133 +
x86/has software guard extensionstrue +