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Difference between revisions of "intel/celeron/g3900"
< intel‎ | celeron

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{{mpu
 
{{mpu
 
|name=Celeron G3900
 
|name=Celeron G3900
 +
|image=skylake (fclga1151).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
Line 9: Line 10:
 
|s-spec=SR2HV
 
|s-spec=SR2HV
 
|market=Desktop
 
|market=Desktop
 +
|first announced=October 19, 2015
 +
|first launched=October 19, 2015
 +
|release price=$42.00
 
|family=Celeron
 
|family=Celeron
 
|series=3000
 
|series=3000
 
|locked=Yes
 
|locked=Yes
 
|frequency=2,800 MHz
 
|frequency=2,800 MHz
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 +
|clock multiplier=28
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
 
|microarch=Skylake
 
|microarch=Skylake
 +
|chipset=Sunrise Point
 
|core name=Skylake S
 
|core name=Skylake S
 
|core family=6
 
|core family=6
 +
|core model=94
 
|core stepping=S0
 
|core stepping=S0
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
 +
|die area=98.57 mm²
 +
|die length=10.3 mm
 +
|die width=9.57 mm
 
|word size=64 bit
 
|word size=64 bit
 
|core count=2
 
|core count=2
 
|thread count=2
 
|thread count=2
 
|max cpus=1
 
|max cpus=1
 +
|max memory=64 GiB
 +
|v core min=0.55 V
 +
|v core max=1.52 V
 +
|tdp=51 W
 +
|tjunc min=0 °C
 +
|tjunc max=100 °C
 +
|tstorage min=-25 °C
 +
|tstorage max=125 °C
 
|package module 1={{packages/intel/fclga-1151}}
 
|package module 1={{packages/intel/fclga-1151}}
 
}}
 
}}

Revision as of 07:54, 8 July 2017

Template:mpu

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB write-back
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Facts about "Celeron G3900 - Intel"
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l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +