From WikiChip
Difference between revisions of "intel/celeron/g3920"
Line 14: | Line 14: | ||
|isa family=x86 | |isa family=x86 | ||
|microarch=Skylake | |microarch=Skylake | ||
+ | |core name=Skylake S | ||
|core family=6 | |core family=6 | ||
|process=14 nm | |process=14 nm |
Revision as of 12:48, 7 July 2017
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Facts about "Celeron G3920 - Intel"
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |