From WikiChip
Difference between revisions of "intel/celeron/3955u"
m (Bot: Automated text replacement (-\| electrical += Yes +)) |
|||
Line 1: | Line 1: | ||
{{intel title|3955U}} | {{intel title|3955U}} | ||
{{mpu | {{mpu | ||
− | | name | + | |name=Celeron 3955U |
− | | no image | + | |no image=Yes |
− | | image | + | |image=skylake (bga1356).png |
− | + | |designer=Intel | |
− | + | |manufacturer=Intel | |
− | | designer | + | |model number=3955U |
− | | manufacturer | + | |s-spec=SR2EW |
− | | model number | + | |market=Mobile |
− | | | + | |first announced=August 15, 2015 |
− | | market | + | |first launched=December 27, 2015 |
− | | first announced | + | |family=Celeron |
− | | first launched | + | |series=3000 |
− | + | |locked=Yes | |
− | + | |frequency=2,000 MHz | |
− | + | |bus type=OPI | |
− | | family | + | |bus rate=4 GT/s |
− | | series | + | |clock multiplier=20 |
− | | locked | + | |isa=x86-64 |
− | | frequency | + | |isa family=x86 |
− | | | + | |microarch=Skylake |
− | | | + | |core name=Skylake U |
− | | | + | |core family=6 |
− | | | + | |core model=78 |
− | | | + | |core stepping=D1 |
− | | | + | |process=14 nm |
− | | | + | |transistors=1,750,000,000 |
− | | | + | |technology=CMOS |
− | | | + | |die area=98.57 mm² |
− | + | |die length=10.3 mm | |
− | | | + | |die width=9.57 mm |
− | | | + | |mcp=Yes |
− | | | + | |die count=2 |
− | | | + | |word size=64 bit |
− | | | + | |core count=2 |
− | | | + | |thread count=2 |
− | | | + | |max cpus=1 |
− | | die | + | |max memory=32 GiB |
− | | word size | + | |tdp=15 W |
− | | core count | + | |ctdp down=10 W |
− | | thread count | + | |temp max=100 °C |
− | | max cpus | + | |tjunc min=0 °C |
− | | max memory | + | |tjunc max=100 °C |
− | + | |tstorage min=-25 °C | |
− | + | |tstorage max=125 °C | |
− | | tdp | ||
− | | ctdp down | ||
− | | | ||
− | | | ||
− | | | ||
− | |||
|package module 1={{packages/intel/fcbga-1356}} | |package module 1={{packages/intel/fcbga-1356}} | ||
}} | }} |
Revision as of 17:38, 3 July 2017
Template:mpu The Intel Celeron 3955U is a dual-core 64-bit mobile microprocessor released by Intel in the third quarter of 2015. The 3955U is designed to replace the Broadwell-based celeron. Manufactured using 14nm process, the Skylake-based 3955U Celeron processor can be configured to run at down to 10 Watt TDP. This processor, just like its predecessor lack support for any of Intel's advanced technologies such as hyper-threading, trusted execution, transactional synchronization extensions (TSX), and turbo-boost.
Cache
- Main article: Skylake § Cache
Cache Info [Edit Values] | ||
L1I$ | 64 KiB 65,536 B 0.0625 MiB |
2x32 KiB |
L1D$ | 64 KiB 65,536 B 0.0625 MiB |
2x32 KiB |
L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB |
2x256 KiB 4-way set associative |
L3$ | 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB |
Graphics
Integrated Graphic Information | |
GPU | Intel HD Graphics 510 |
Displays | 3 |
Frequency | 300 MHz 0.3 GHz
300,000 KHz |
Max frequency | 900 MHz 0.9 GHz
900,000 KHz |
Max memory | 1700 MiB 1,740,800 KiB
1,782,579,200 B 1.66 GiB |
Output | DisplayPort, Embedded DisplayPort, HDMI, DVI |
DirectX | 12 |
OpenGL | 4.4 |
Max HDMI Res | 4096x2304 @24 Hz |
Max DP Res | 4096x2304 @60 Hz |
Max eDP Res | 4096x2304 @60 Hz |
Memory controller
Integrated Memory Controller | |
Type | DDR4-1866, DDR4-2133, LPDDR3-1600, LPDDR3-1866 |
Controllers | 1 |
Channels | 2 |
Max bandwidth | 34,100 MB/s |
Max memory | 32,768 MB |
Expansions
Features
Facts about "Celeron 3955U - Intel"
has feature | integrated gpu + |
integrated gpu | Intel HD Graphics 510 + |
integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
integrated gpu max frequency | 900 MHz (0.9 GHz, 900,000 KHz) + |
integrated gpu max memory | 1,700 MiB (1,740,800 KiB, 1,782,579,200 B, 1.66 GiB) + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |