Difference between revisions of "intel/xeon e5/e5-2679 v4"

From WikiChip

< intel‎ | xeon e5

Revision as of 17:44, 30 June 2017

Template:mpu The Xeon E5-2679 v4 is a 64-bit icosa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for 2S environments. Operating at 2.5 GHz with a turbo boost frequency of 3.3 GHz for a single active core, this MPU has a TDP of 200 W and is manufactured on a 14 nm process (based on Broadwell).

1 Cache
2 Graphics
3 Memory controller
4 Expansions
5 Features

Cache

Main article: Broadwell § Cache

Cache Info [Edit Values]
L1I$	640 KiB 655,360 B 0.625 MiB	20x32 KiB 8-way set associative (per core, write-back)
L1D$	640 KiB 655,360 B 0.625 MiB	20x32 KiB 8-way set associative (per core, write-back)
L2$	5 MiB 5,120 KiB 5,242,880 B 0.00488 GiB	20x256 KiB 8-way set associative (per core, write-back)
L3$	50 MiB 51,200 KiB 52,428,800 B 0.0488 GiB	20x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type	DDR4-2400
Controllers	1
Channels	4
ECC Support	Yes
Max bandwidth	71.53 GiB/s
Bandwidth (single)	17.88 GiB/s
Bandwidth (dual)	35.76 GiB/s
Max memory	1,536 GiB
Physical Address Extensions	46 bit

Expansions

Template:mpu expansions

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2679_v4&oldid=49642"

Facts about "Xeon E5-2679 v4 - Intel"

RDF feed

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon E5-2679 v4 - Intel#io +
base frequency	2,500 MHz (2.5 GHz, 2,500,000 kHz) +
bus links	2 +
bus rate	9,600 MT/s (9.6 GT/s, 9,600,000 kT/s) +
bus speed	4,800 MHz (4.8 GHz, 4,800,000 kHz) +
bus type	QPI +
chipset	C610 Series +
clock multiplier	25 +
core count	20 +
core family	6 +
core model	4F +
core name	Broadwell EP +
core stepping	B0 +
core voltage	1.82 V (18.2 dV, 182 cV, 1,820 mV) +
cpuid	406F1 +
designer	Intel +
die area	456.12 mm² (0.707 in², 4.561 cm², 456,120,000 µm²) +
family	Xeon E5 +
first announced	June 20, 2016 +
first launched	June 20, 2016 +
full page name	intel/xeon e5/e5-2679 v4 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has extended page tables support	true +
has feature	Trusted Execution Technology +, Transactional Synchronization Extensions +, Intel vPro Technology +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology + and Extended Page Tables +
has intel enhanced speedstep technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
io voltage	1.2 V (12 dV, 120 cV, 1,200 mV) +
io voltage tolerance	3% +
l1d$ description	8-way set associative +
l1d$ size	640 KiB (655,360 B, 0.625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	640 KiB (655,360 B, 0.625 MiB) +
l2$ description	8-way set associative +
l2$ size	5 MiB (5,120 KiB, 5,242,880 B, 0.00488 GiB) +
l3$ description	20-way set associative +
l3$ size	50 MiB (51,200 KiB, 52,428,800 B, 0.0488 GiB) +
ldate	June 20, 2016 +
manufacturer	Intel +
market segment	Server +
max cpu count	2 +
max memory	1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max pcie lanes	40 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Broadwell +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	E5-2679 v4 +
name	Xeon E5-2679 v4 +
part number	CM8066002647800 +
platform	Grantley EP 2S +
process	14 nm (0.014 μm, 1.4e-5 mm) +
s-spec	SR2K5 +
series	E5-2000 +
smp max ways	2 +
tdp	200 W (200,000 mW, 0.268 hp, 0.2 kW) +
technology	CMOS +
thread count	40 +
transistor count	7,200,000,000 +
turbo frequency (10 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (11 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (12 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (13 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (14 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (15 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (16 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (17 cores)	3,200 MHz +
turbo frequency (18 cores)	3,200 MHz +
turbo frequency (19 cores)	3,200 MHz +
turbo frequency (1 core)	3,300 MHz (3.3 GHz, 3,300,000 kHz) +
turbo frequency (20 cores)	3,200 MHz +
turbo frequency (2 cores)	3,300 MHz (3.3 GHz, 3,300,000 kHz) +
turbo frequency (3 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (4 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (5 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (6 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (7 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (8 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (9 cores)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

@@ Line 10: / Line 10: @@
 | model number        = E5-2679 v4
 | part number         = CM8066002647800
-| part number 1       =
 | part number 2       =
 | part number 3       =
+| part number 4       =
 | market              = Server
 | first announced     = June 20, 2016

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas